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參數(shù)資料
| 型號： | DS1743 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Y2KC Nonvolatile Timekeeping RAM(Y2KC非易失性計時RAM) |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 152K |
| 代理商： | DS1743 |
DS1743/DS1743P
052198 4/17
DS1743 REGISTER MAP
Table 2
ADDRESS
DATA
FUNCTION/RANGE
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
1FFF
10 YEAR
YEAR
YEAR
00–99
1FFE
X
X
X
10 MO
MONTH
MONTH
01–12
1FFD
X
X
10 DATE
DATE
DATE
01–31
1FFC
BF
FT
X
X
X
DAY
DAY
01–07
1FFB
X
X
10 HOUR
HOUR
HOUR
00–23
1FFA
X
10 MINUTES
MINUTES
MINUTES
00–59
1FF9
OSC
10 SECONDS
SECONDS
SECONDS
00–59
1FF8
W
R
10 CENTURY
CENTURY
CENTURY
00–39
OSC = STOP BIT
W
= WRITE BIT
R
X
=
=
READ BIT
SEE NOTE BELOW
FT =
BF =
FREQUENCY TEST
BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output
enable) is low, WE (write enable) is high, and CE (chip
enable) is low. The device architecture allows ripple-
through access to any of the address locations in the NV
SRAM. Valid data will be available at the DQ pins within
t
AA
after the last address input is stable, providing that
the CE, and OE access times and states are satisfied. If
CE, or OE access times and states are not met, valid
data will be available at the latter of chip enable access
(t
CEA
) or at output enable access time (t
OEA
). The state
of the data input/output pins (DQ) is controlled by CE,
and OE. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the
address inputs are changed while CE, and OE remain
valid, output data will remain valid for output data hold
time (t
OH
) but will then go indeterminate until the next
address access.
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever WE, and CE
are in their active state. The start of a write is referenced
to the latter occurring transition of WE, on CE. The ad-
dresses must be held valid throughout the cycle. CE, or
WE must return inactive for a minimum of t
WR
prior to
the initiation of another read or write cycle. Data in must
be valid t
DS
prior to the end of write and remain valid for
t
DH
afterward. In a typical application, the OE signal will
be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by
the address inputs. A low transition on WE will then dis-
able the outputs t
WEZ
after WE goes active.
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| DS1743-100 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743-100 IND | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743-100+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743-100IND | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743-100IND+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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