參數(shù)資料
型號(hào): DS1708
廠商: Maxim Integrated Products, Inc.
英文描述: 3.3 and 5.0 Volt MicroMonitor(3.3和5.0 V微監(jiān)控器(手復(fù)+電源比較器))
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 66K
代理商: DS1708
DS1707/DS1708
022698 2/10
The third function the DS1707/DS1708 performs is
pushbutton reset control. The DS1707/DS1708
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
OPERATION
Power Monitor
The DS1707/DS1708 detects out–of–tolerance power
supply conditions and warns a processor–based sys-
tem of impending power failure. When V
CC
falls below
the minimum V
CC
tolerance, a comparator outputs the
RST and RST signals. RST and RST are excellent con-
trol signals for a microprocessor, as processing is
stopped at the last possible moment of valid V
CC
. On
power–up, RST and RST are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
Pushbutton Reset
The DS1707/DS1708 provides an input pin for direct
connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that
RST and RST signals of at least 130 ms minimum will be
generated. The 130 ms delay commences as the push-
button reset input is released from the low level. The
pushbutton can be initiated by connecting the NMI out-
put to the PBRST input as shown in Figure 3.
Non–Maskable Interrupt
The DS1707/DS1708 generates a non–maskable inter-
rupt (NMI) for early warning of a power failure. A preci-
sion comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an inter-
nal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point V
TP
is 1.25 volts, the proper val-
ues for R1 and R2 can be determined by the equation as
shown in Figure 5. Proper operation of the
DS1707/DS1708 requires that the voltage at the IN pin
be limited to V
CC
. Therefore, the maximum allowable
voltage at the supply being monitored (V
MAX
) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply sys-
tem, maximizing the amount of time for system shut–
down between NMI and RST/RST.
When the supply being monitored decays to the voltage
sense point, the DS1707/DS1708 pulses the NMI out-
put to the active state for a minimum 200
μ
s. The NMI
power fail detection circuitry also has built–in hysteresis
of 100
μ
V. The supply must be below the voltage sense
point for approximately 5
μ
s before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false inter-
rupts. During a power–up, any detected IN pin levels
below V
TP
by the comparator are disabled from gener-
ating an interrupt until V
CC
rises to V
CCTP
. As a result,
any potential NMI pulse will not be initiated until V
CC
reaches V
CCTP
.
Connecting NMI to PBRST would allow the non–mask-
able interrupt to generate an automatic reset when an
out–of–tolerance condition occurred in a monitored
supply. An example is shown in Figure 3.
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