
DS1543
070198 5/19
WDS = Watchdog Steering bit
BMB0–BMB4 = Watchdog Multiplier bits
RB0–RB1 = Watchdog Resolution bits
AF = Alarm Flag
0 = “0” and are read only
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To
increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize cur-
rent drain from the battery. The OSC bit is the MSB of
the seconds register (B7 of 1FF9h). Setting it to a “1”
stops the oscillator, setting to a “0” starts the oscillator.
The DS1543 is shipped from Dallas Semiconductor with
the clock oscillator turned off, OSC bit set to a “1”.
READING THE CLOCK
When reading the RTC data, it is recommended to halt
updates to the external set of double buffered RTC reg-
isters. This puts the external registers into a static state
allowing data to be read without register values chang-
ing during the read process. Normal updates to the
internal registers continue while in this state. External
updates are halted when a “1” is written into the read bit,
B6 of the Control register (1FF8h). As long as a “1”
remains in the Control register read bit, updating is
halted. After a halt is issued, the registers reflect the
RTC count (day, date, and time) that was current at the
moment the halt command was issued. Normal
updates to the external set of registers will resume
within 1 second after the read bit is set to a “0”.
SETTING THE CLOCK
The eighth bit, B7 of the control register is the write bit.
Setting the write bit to a “1”, like the read bit, halts
updates to the DS1543 (1FF8h–1FFFh) registers. After
setting the write bit to a “1”, RTC registers can be loaded
with the desired RTC count (day, date, and time) in 24
hour BCD format. Setting the write bit to a “0” then trans-
fers the values written to the internal RTC registers and
allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1543 is guaranteed to keep time accuracy to
within
±
1 minute per month at 25
°
C. The RTC is cali-
brated at the factory by Dallas Semiconductor using
nonvolatile tuning elements. The DS1543 does not
require additional calibration and, in most applications,
temperature deviations will have a negligible effect on
accuracy. For this reason, methods of field clock cal-
ibration are not available and not necessary. Attempts
to calibrate the RTC that may be used with similar
device types (M48T5x family) will not have any effect
even though the DS1543 appears to accept calibration
data.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1543 and DS9034PCX are each individually
tested for accuracy. Once mounted together, the mod-
ule is guaranteed to keep time accuracy to within
±
1.53
minutes per month (35 ppm) at 25
°
C.
FREQUENCY TEST MODE
The DS1543 frequency test mode uses the open drain
IRQ/FT output. With the oscillator running, the IRQ/FT
output will toggle at 512 Hz when the FT bit is a “1”, the
Alarm Flag Enable bit (AE) is a “0”, and the Watchdog
Steering bit (WDS) is a “1” or the Watchdog Register is
reset (register 1FF7h = 00h). The IRQ/FT output and
the frequency test mode can be used as a measure of
the actual frequency of the 32.768 KHz RTC oscillator.
The IRQ/FT pin is an open drain output which requires a
pull–up resistor for proper operation. The FT bit is
cleared to a “0” on power–up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1543 reside
within registers 1FF2h – 1FF5h. Register 1FF6h con-
tains two alarm enable bits: Alarm Enable (AE) and
Alarm in Backup Enable (ABE). The AE and ABE bits
must be set as described below for the IRQ/FT output to
be activated for a matched alarm condition.
The alarm can be programmed to activate on a specific
day of the month or repeat every day, hour, minute, or
second. It can also be programmed to go off while the
DS1543 is in the battery backed state of operation to
serve as a system wake–up. Alarm mask bits
AM1–AM4 control the alarm mode. Table 3 shows the
possible settings. Configurations not listed in the table
default to the once per second mode to notify the user of
an incorrect alarm setting.