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參數(shù)資料
| 型號(hào)： | DS1486P |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RAMified Watchdog Timekeeper(RAM化的看門狗計(jì)時(shí)器) |
| 中文描述： | RAMified看門狗計(jì)時(shí)器 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 174K |
| 代理商： | DS1486P |
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DS1486P
070298 2/16
DESCRIPTION
The DS1486 is a nonvolatile Static RAM with a full func-
tion Real Time Clock (RTC), alarm, watchdog timer, and
interval timer which are all accessible in a Byte–wide
format. The DS1486 contains a lithium energy source
and a quartz crystal which eliminates the need for any
external circuitry. Data contained within 128K by 8–bit
memory and the timekeeping registers can be read or
written in the same manner as bytewide static RAM.
The timekeeping registers are located in the first 14 by-
tes of memory space. Data is maintained in the RAMi-
fied Timekeeper by intelligent control circuitry which de-
tects the status of V
CC
and write protects memory when
V
CC
is out of tolerance. The lithium energy source can
maintain data and real time for over ten years in the ab-
sence of V
CC
. Timekeeper information includes hun-
dredths of seconds, seconds, minutes, hours, day,
date, month, and year. The date at the end of the month
is automatically adjusted for months with less than 31
days, including correction for leap year. The RAMified
Timekeeper operates in either 24 hour or 12 hour format
with an AM/PM indicator. The watchdog timer provides
alarm interrupts and interval timing between 0.01 sec-
onds and 99.99 seconds. The real time alarm provides
for preset times of up to one week. Interrupts for both
watchdog and RTC will operate when system is pow-
ered down. Either can provide system “wake-up” sig-
nals.
PACKAGES
The DS1486 is available in two packages (32–pin DIP
module and 34–pin PowerCap module). The 32–pin
Dip style module integrates the crystal, lithium energy
source, and silicon all in one package. The 32–pin
PowerCap Module Board is designed with contacts for
connection to a separate PowerCap (DS90934PCX)
that contains the crystal and battery. The design allows
the PowerCap to be mounted on top of the DS1486P
after the completion of the surface mount process.
Mounting the PowerCap after the surface mount pro-
cess prevents damage to the crystal and battery due to
high temperatures required for solder reflow. The Pow-
erCap is keyed to prevent reverse insertion. The Pow-
erCap Module Board and PowerCap are ordered sepa-
rately and shipped in separate containers. The part
number for the PowerCap is DS9034PCX.
OPERATION – READ REGISTERS
The DS1486 executes a read cycle whenever WE
(Write Enable) is inactive (High), CE (Chip Enable) and
OE (Output Enable) are active (Low). The unique ad-
dress specified by the address inputs (A0–A16) defines
which of the registers is to be accessed. Valid data will
be available to the eight data output drivers within t
ACC
(Access Time) after the last address input signal is
stable, providing that CE and OE access times are also
satisfied. If OE and CE access times are not satisfied,
then data access must be measured from the latter oc-
curring signal (CE or OE) and the limiting parameter is
either t
CO
for CE or t
OE
for OE rather than address ac-
cess.
OPERATION – WRITE REGISTERS
The DS1486 is in the write mode whenever the WE
(Write Enable) and CE (Chip Enable) signals are in the
active (Low) state after the address inputs are stable.
The latter occurring falling edge of CE or WE will deter-
mine the start of the write cycle. The write cycle is termi-
nated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle.
WE must return to the high state for a minimum recovery
state (t
WR
) before another cycle can be initiated. Data
must be valid on the data bus with sufficient Data Set-Up
(t
DS
) and Data Hold Time (t
DH
) with respect to the earlier
rising edge of CE or WE. The OE control signal should
be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been en-
abled (CE and OE active), then WE will disable the out-
puts in t
ODW
from its falling edge.
DATA RETENTION
The RAMified Timekeeper provides full functional capa-
bility when V
CC
is greater than 4.5 volts and write–pro-
tects the register contents at 4.25 volts typical. Data is
maintained in the absence of V
CC
without any additional
support circuitry. The DS1486 constantly monitors V
CC
.
Should the supply voltage decay, the RAMified Time-
keeper will automatically write-protect itself and all in-
puts to the registers become “don’t care”. The two inter-
rupts INTA and INTB (INTB) and the internal clock and
timers continue to run regardless of the level of V
CC
.
However, it is important to insure that the pull–up resis-
tors used with the interrupt pins are never pulled up to a
value that is greater than V
CC
+ 0.3V. As V
CC
falls below
approximately 3.0 volts, a power switching circuit turns
the internal lithium energy source on to maintain the
clock and timer data functionality. It is also required to
insure that during this time (battery backup mode), the
voltage present at INTA and INTB (INTB) does never
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參數(shù)描述 |
|---|---|
| DS1486P-120 | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1486P-120+ | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1486P-150 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:RAMified Watchdog Timekeeper |
| DS1487 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Power RS-485 1⁄4 Unit Load Multipoint Transceiver |
| DS1487M | 功能描述:RS-422/RS-485 接口 IC RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)速率:1136 Kbps 工作電源電壓:3 V to 5.5 V 電源電流:5.9 mA 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-28 封裝:Tube |
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