參數(shù)資料
型號: DS1486
廠商: Maxim Integrated Products, Inc.
英文描述: RAMified Watchdog Timekeeper(RAM化的看門狗計時器)
中文描述: RAMified看門狗計時器
文件頁數(shù): 5/16頁
文件大?。?/td> 174K
代理商: DS1486
DS1486P
070298 5/16
TIME OF DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day
data in BCD. Ten bits within these eight registers are not
used and will always read zero regardless of how they
are written. Bits 6 and 7 in the Months Register (9) are
binary bits. When set to logic zero, EOSC (Bit 7) en-
ables the real time clock oscillator. This bit is set to logic
one as shipped from Dallas Semiconductor to prevent
lithium energy consumption during storage and ship-
ment (DIP Module only). This bit will normally be turned
on by the user during device initialization. However, the
oscillator can be turned on and off as necessary by set-
ting this bit to the appropriate level. The INTA and
Square Wave Output signals are tied together at pin 30
on the 32–pin DIP module. With this package, bit 6 of
the Months Register (9) controls the function of this pin.
When set to logic zero, the pin will output a 1024 Hz
square wave signal. When set to logic one, the pin is
available for interrupt A output (INTA) only. The INTA
and Square Wave Output signals are separated on the
34–pin PowerCap module. With this package, bit 6 of
the Months Register (9) controls only the Square Wave
Output (pin 33). When set to logic zeros, pin 33 will out-
put a 1024 Hz square wave signal. When set to logic
one, pin 33 is in a high impedance state. Pin 34 (INTA) is
not affected by the setting of bit 6. Bit 6 of the Hours reg-
ister is defined as the 12 or 24 hour select bit. When set
to logic one, the 12 hour format is selected. In the 12
hour format, bit 5 is the AM/PM bit with logic one being
PM. In the 24 hour mode, bit 5 is the second 10 hour bit
(20–23 hours). The Time of Day registers are updated
every 0.01 seconds from the Real Time Clock, except
when the TE bit (bit 7 of Register B) is set low or the
clock oscillator is not running. The preferred method of
synchronizing data access to and from the RAMified
Timekeeper is to access the Command register by do-
ing a write cycle to address location 0B and setting the
TE bit (Transfer Enable bit) to a logic zero. This will
freeze the External Time of Day registers at the present
recorded time, allowing access to occur without danger
of simultaneous update. When the watch registers have
been read or written, a second write cycle to location
0B, setting the TE bit to a logic one, will put the Time of
Day Registers back to being updated every 0.01 sec-
ond. No time is lost in the real time clock because the
internal copy of the Time of Day register buffers is con-
tinually incremented while the external memory regis-
ters are frozen. An alternate method of reading and writ-
ing the Time of Day registers is to ignore
synchronization. However, any single read may give er-
roneous data as the real time clock may be in the pro-
cess of updating the external memory registers as data
is being read. The internal copies of seconds through
years are incremented, and the Time of Day Alarm is
checked during the period that hundreds of seconds
reads 99 and are transferred to the external register
when hundredths of seconds roll from 99 to 00. A way of
making sure data is valid is to do multiple reads and
compare. Writing the registers can also produce erro-
neous results for the same reasons. A way of making
sure that the write cycle has caused proper update is to
do read verifies and re–execute the write cycle if data is
not correct. While the possibility of erroneous results
from reads and write cycles has been stated, it is worth
noting that the probability of an incorrect result is kept to
a minimum due to the redundant structure of the RAMi-
fied Timekeeper.
TIME OF DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the Time of Day Alarm
Registers. Bits 3, 4, 5, and 6 of Register 7 will always
read zero regardless of how they are written. Bit 7 of
Registers 3, 5, and 7 are mask bits (Figure 3). When all
of the mask bits are logic zero, a Time of Day Alarm will
only occur when Registers 2, 4, and 6 match the values
stored in Registers 3, 5, and 7. An alarm will be gener-
ated every day when bit 7 of Register 7 is set to a logic
one. Similarly, an alarm is generated every hour when
bit 7 of Registers 7 and 5 is set to a logic 1. When bit 7 of
Registers 7, 5, and 3 is set to a logic 1, an alarm will
occur every minute when Register 1 (seconds) rolls
from 59 to 00.
Time of Day Alarm Registers are written and read in the
same format as the Time of Day Registers. The Time of
Day Alarm Flag and Interrupt are always cleared when
Alarm Registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog
Alarm. The two registers contain a time count from
00.01 to 99.99 seconds in BCD. The value written into
the Watchdog Alarm Registers can be written or read in
any order. Any access to Register C or D will cause the
Watchdog Alarm to reinitialize and clears the Watchdog
Flag Bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers are
read, the Watchdog Timer will start counting down from
the entered value to zero. When zero is reached, the
Watchdog Interrupt Output will go to the active state.
The Watchdog Timer Countdown is interrupted and re-
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