參數(shù)資料
型號(hào)： DS14285SN
英文描述： Real Time Clock with NV RAM Control
中文描述： 實(shí)時(shí)時(shí)鐘的非易失RAM控制
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 303K
代理商： DS14285SN
DS14285/DS14287
4 of 25
R/
W
(Read/Write Input) -
The R/
W
pin also has two modes of operation. When the MOT pin is
connected to V
CC
for Motorola timing, R/
W
is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/
W
while DS is high. A write cycle is
indicated when R/
W
is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/
W
signal is an active low signal called
WR
. In this mode the R/
W
pin has the same meaning as the Write Enable signal (
WE
) on generic
RAMs.
CS
(Chip Select Input) -
The Chip Select signal must be asserted low for a bus cycle in the
DS14285/DS14287 to be accessed.
CS
must be kept in the active state during DS for Motorola timing
and during
RD
and
WR
for Intel timing. Bus cycles which take place without asserting
CS
will latch
addresses but no access will occur. When V
CC
is below 4.25 volts, the DS14285/DS14287 internally
inhibits access cycles by internally disabling the
CS
input. This action protects both the real time clock
data and RAM data during power outages.
IRQ
(Interrupt Request Output) -
The
IRQ
pin is an active low output of the DS14285/DS14287 that
can be used as an interrupt input to a processor. The
IRQ
output remains low as long as the status bit
causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the
IRQ
pin the
processor program normally reads the C register. The
RESET
pin also clears pending interrupts.
When no interrupt conditions are present, the
IRQ
level is in the high impedance state. Multiple
interrupting devices can be connected to an
IRQ
bus. The
IRQ
bus is an open drain output and requires an
external pull-up resistor.
RESET
(Reset Input) -
The
RESET
pin has no effect on the clock, calendar, or RAM. On power-up the
RESET
pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
that
RESET
is held low is dependent on the application. However, if
RESET
is used on power-up, the
time
RESET
is low should exceed 200 ms to make sure that the internal timer that controls the
DS14285/DS14287 on power-up has timed out. When
RESET
is low and V
CC
is above 4.25 volts, the
following occurs:
A.
Periodic Interrupt Enable (PEI) bit is cleared to 0.
B.
Alarm Interrupt Enable (AIE) bit is cleared to 0.
C.
Update Ended Interrupt Flag (UF) bit is cleared to 0.
D.
Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E.
Periodic Interrupt Flag (PF) bit is cleared to 0.
F.
The device is not accessible until
RESET
is returned high.
G.
Alarm Interrupt Flag (AF) bit is cleared to 0.
H.
IRQ
pin is in the high impedance state.
I.
Square Wave Output Enable (
SQWE
) bit is cleared to 0.
J.
Update Ended Interrupt Enable (UIE) is cleared to 0.
K.
CEO
is driven high.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS14285SN/T&R 制造商:Maxim Integrated Products 功能描述:IC RTC W/NV RAM CNTRL IND 24SOIC
DS14285SN/T&R 功能描述:IC RTC W/NV RAM CNTRL IND 24SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件
DS14285SN/TR 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Real-Time Clock with NV RAM
DS14285SN+ 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS14285SN+T&R 制造商:Maxim Integrated Products 功能描述:IC RTC W/NV RAM CNTRL 24-SOIC 制造商:DSC 功能描述:
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