- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9330 > DS1384FP-12 (Maxim Integrated Products)IC CTRLR RTC WDOG 120NS 44-MQFP PDF資料下載
參數(shù)資料
| 型號： | DS1384FP-12 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR RTC WDOG 120NS 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出，監(jiān)視計時器 |
| 存儲容量： | 50B |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.4 V ~ 4 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | DS1384FP12 |
DS1384
9 of 18
TIME-OF-DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the time of day alarm registers. Bits 3, 4, 5, and 6 of register 7 will always
read 0 regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Table 1). When all
of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the
values stored in registers 3, 5, and 7. An alarm will be generated every day when bit 7 of register 7 is set
to a logic 1. Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1.
When bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1
(seconds) rolls from 59 to 00.
Time of day alarm registers are written and read in the same format as the time of day registers. The time
of day alarm flag and interrupt is always cleared when alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from
00.01 seconds to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be
written or read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize
and clears the Watchdog Flag Bit and the Watchdog Interrupt Output. When a new value is entered or the
Watchdog Registers are read, the Watchdog Timer will start counting down from the entered value to 0.
When 0 is reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer
Countdown is interrupted and reinitialized back to the entered value every time either of the registers are
accessed. In this manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog
Alarm from ever going to an active level. If access does not occur, countdown alarm will be repetitive.
The Watchdog Alarm Registers always read the entered value. The actual count down register is internal
and is not readable. Writing registers C and D to 0 will disable the Watchdog Alarm feature.
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
Bit 7: TE (Transfer Enable). This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
Bit 6: IPSW (Interrupt Switch). When set to a logic 1,
INTA is the Time of Day Alarm and
INTB/(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now
the Watchdog Alarm output and
INTB /(INTB) is the Time of Day Alarm output.
Bit 5: IBH/LO (Interrupt B Sink or Source Current). When this bit is set to a logic 1 and VCC is
applied,
INTB /(INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0,
INTB will sink current (see DC characteristics IOL).
Bit 4: PU/LVL (Interrupt Pulse Mode or Level Mode). This bit determines whether both interrupts
will output a pulse or level signal. When set to a logic 0,
INTA and INTB /(INTB) will be in the level
mode. When this bit is set to a logic 1, the pulse mode is selected and
INTA will sink current for a
minimum of 3 ms and then release.
INTB /(INTB) will either sink or source current, depending on the
condition of bit 5, for a minimum of 3 ms and then release.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-2NR-MY-F3 | CONVERTER MOD DC/DC 7.5V 50W |
| VE-BN4-IU-F2 | CONVERTER MOD DC/DC 48V 200W |
| DS1305E | IC RTC SERIAL ALARM 20-TSSOP |
| VE-BN4-IU-F1 | CONVERTER MOD DC/DC 48V 200W |
| VI-2NP-MY-F4 | CONVERTER MOD DC/DC 13.8V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1384FP-12+ | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1384FP-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1384T-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1384T-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1385 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:RAMified Real Time Clock 4K x 8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。