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參數(shù)資料
| 型號(hào)： | DS1384FP-12 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR RTC WDOG 120NS 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，方波輸出，監(jiān)視計(jì)時(shí)器 |
| 存儲(chǔ)容量： | 50B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.4 V ~ 4 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | DS1384FP12 |
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DS1384
3 of 18
PIN
NAME
FUNCTION
13, 14, 15,
17–21
DQ0, DQ1, DQ2,
DQ3–DQ7
Data Bus (Bidirectional). When a qualified address from 00000H–
0003FH is presented to the device, data is passed to or from the on-
chip 64 timekeeping/RAM registers via the data bus lines. Data is
written on the rising edge of
WE when CE is active. If CE is active
without
WE, data is read from the device and driven onto the data bus
pins when
OE is low.
16, 41, 44
GND
Ground. DC power input.
22
CEO
Active-Low RAM Chip-Enable Output. When power is good, the
CE
input is passed through to
CEO. If VCC is below VPF, CEO remains at
an inactive high level.
23
OER
Active-Low RAM Output Enable (Output). When power is good and
the address value is not within the range of 00000H and 0003FH, and
CE is active, the OE input is passed through to OER. If these
conditions are not met,
OER remains at an inactive high level.
24
CE
Active-Low Chip Enable (Input). This signal must be asserted low
during a bus cycle to access the on-chip timekeeping RAM registers,
or to access the external RAM via
CEO.
26
OE
Active-Low Output Enable (Input). This signal identifies the time
period when either the RTC or the external SRAM drives the bus with
read data, provided that
CE is valid with WE disabled. When one of
the 64 on-chip registers is selected during a read cycle, the
OE is the
enable signal for the DS1384 output buffers and the data bus is driven
with read data. When the external RAM is selected during a read
cycle, the
OE signal is passed through to the OER pin so that read data
is driven by the external SRAM.
31
WE
Active-Low Write Enable (Input). This signal identifies the time
period during which data is written to either the on-chip registers or to
an external SRAM location. When one of the on-chip 64 registers is
addressed, data is written to the selected register on the rising edge of
WE.
32, 34
VBAT1, VBAT2
Battery Inputs for Any Standard 3V Lithium Cell or Other Energy
Source. Battery voltage must be held between 2.4V and 4V for proper
operation. In the absence of power, the DS1384 has a maximum load
of 0.5
drawn from the external RAM in standby mode at +25
°C to size the
external energy source. The DS1384 samples VBAT1 and VBAT2 and
always selects the battery with the higher voltage. If only one battery
is used, the unused battery input must be grounded.
35
PFO
Power-Fail Signal (Output, Active Low when VWP Occurs). High state
occurs tREC after power-up and VCC ≥ 4.5V.
36
SQW
Square-Wave Output. This pin can be programmed to output a
1024Hz square-wave signal. When the signal is turned off, the pin is
high impedance.
37
VCCO
Switched DC Power for SRAM (Output). This pin is connected to VCC
when VCC voltage is above VSO (the greater of VBAT1 or VBAT2). When
VCC voltage falls below this level, VCCO is connected to the higher
voltage battery pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1384FP-12+ | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1384FP-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1384T-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1384T-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1385 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:RAMified Real Time Clock 4K x 8 |
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