
DS1345Y/AB
2 of 12
READ MODE
The DS1345 devices execute a read cycle whenever 
WE
  (Write Enable) is inactive (high) and 
CE
  (Chip
Enable) and 
OE
 (Output Enable) are active (low). The unique address specified by the 17 address inputs
(A
0
 - A
16
) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
 (Access Time) after the last address input signal is stable, providing
that 
CE
  and 
OE
 (Output Enable) access times are also satisfied. If 
OE
 and 
CE
  access times are not
satisfied, then data access must be measured from the later-occurring signal (
CE
  or 
OE
) and the limiting
parameter is either t
CO
 for 
CE
  or t
OE
 for 
OE
 rather than address access.
WRITE MODE
The DS1345 devices execute a write cycle whenever the 
WE
  and 
CE
  signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of 
CE
  or 
WE
  will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of 
CE
  or 
WE
 . All address inputs
must be kept valid throughout the write cycle. 
WE
  must return to the high state for a minimum recovery
time (t
WR
) before another cycle can be initiated. The 
OE
 control signal should be kept inactive (high)
during write cycles to avoid bus contention.  However, if the output drivers are enabled (
CE
  and 
OE
active) then 
WE
  will disable the outputs in t
ODW
 from its falling edge.
DATA RETENTION MODE
The DS1345AB provides full functional capability for V
CC
 greater than 4.75 volts and write protects by
4.5 volts. The DS1345Y provides full functional capability for V
CC
 greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
 without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V
CC
 falls below approximately 2.7 volts, the power switching circuit connects the lithium
energy source to RAM to retain data.  During power-up, when V
CC
 rises above approximately 2.7 volts,
the power switching circuit connects external V
CC
 to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
 exceeds 4.75 volts for the DS1345AB and 4.5 volts for the
DS1345Y.
SYSTEM POWER MONITORING
DS1345 devices have the ability to monitor the external V
CC
 power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting 
RST
 . On power-up, 
RST
  is held active for 200 ms nominal to prevent system
operation during power-on transients and to allow t
REC
 to elapse. 
RST
  has an open drain output driver.
BATTERY MONITORING
The DS1345 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval.  Such monitoring begins within t
REC
 after V
CC
 rises above V
TP
 and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1 M
=
test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output 
BW
 is asserted. Once asserted, 
BW
 remains active until the module is replaced.
The battery is still retested after each V
CC
 power-up, however, even if 
BW
 is active. If the battery voltage
is found to be higher than 2.6V during such testing, 
BW
 is de-asserted and regular 24-hour testing
resumes. 
BW
 has an open drain output driver.