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參數(shù)資料
| 型號： | DS1258WP-150-IND |
| 英文描述： | 3.3V 128k x 16 Nonvolatile |
| 中文描述： | 3.3 128K的× 16非易失 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 167K |
| 代理商： | DS1258WP-150-IND |
DS1258W
8 of 9
NOTES:
1)
WE
is high for a Read Cycle.
2)
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance state.
3)
t
WP
is specified as the logical AND of
CEU
or
CEL
and
WE
. t
WP
is measured from the latter of
CEU
,
CEL
or
WE
going low to the earlier of
CEU
,
CEL
or
WE
going high.
4)
t
DS
is measured from the earlier of
CEU
or
CEL
or
WE
going high.
5)
These parameters are sampled with a 5pF load and are not 100% tested.
6)
If the
CEU
or
CEL
low transition occurs simultaneously with or later than the
WE
low transition in
the output buffers remain in a high impedance state during this period.
7)
If the
CEU
or
CEL
high transition occurs prior to or simultaneously with the
WE
high transition, the
output buffers remain in high impedance state during this period.
8)
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CEU
or
CEL
low
transition, the output buffers remain in a high impedance state during this period.
9)
Each DS1258W has a built-in switch that disconnects the lithium source until V
CC
is first applied by
the user. The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the
time power is first applied by the user.
10)
All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0 to +70 C. For industrial products, this range is -40 C to +85 C.
11)
In a power-down condition the voltage on any pin may not exceed the voltage on V
CC
.
12)
t
WR1
, t
DH1
are measured from
WE
going high.
13)
t
WR2
, t
DH2
are measured from
CEU
OR
CEL
going high.
14)
DS1258W DIP modules are recognized by Underwriters Laboratory (U.L.
) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels:
0.0V to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1258 WP - SSS - III
Operating Temperature Range
blank: 0 to +70 C
IND: -40 to +85 C
Access Speed
100:
150:
100ns
150ns
Package Type
blank: 40-pin (600mil) DIP
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| DS1267-100 | Dual Digital Potentiometer Chip |
| DS1267E-010 | Dual Digital Potentiometer Chip |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1258Y | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:128k x 16 Nonvolatile SRAM |
| DS1258Y/AB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K x 16 Nonvolatile SRAM |
| DS1258Y-100 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1258Y-100# | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1258Y-100-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:128k x 16 Nonvolatile SRAM |
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