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參數(shù)資料
| 型號(hào)： | DS1249AB |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | 2048K Nonvolatile SRAM(2048K 非易失性靜態(tài)RAM) |
| 中文描述： | 256K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP32 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 68K |
| 代理商： | DS1249AB |
DS1249Y/AB
021998 2/9
READ MODE
The DS1249 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 18 address inputs (A
0
–
A
17
) defines which of the 262,144 bytes of data is ac-
cessed. Valid data will be available to the eight data out-
put drivers within t
ACC
(Access Time) after the last ad-
dress input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be mea-
sured from the later occurring signal (CE or OE) and the
limiting parameter is either t
CO
for CE or t
OE
for OE rath-
er than t
ACC
.
WRITE MODE
The DS1249 devices execute a write cycle whenever
the WE and CE signals are active (low) after address in-
puts are stable. The later occurring falling edge of CE or
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1249AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1249Y provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protects
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below ap-
proximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1249AB and 4.5 volts for
the DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than V
TP
, the lithium energy
source is enabled for battery backup operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1249Y | 2048K Nonvolatile SRAM(2048K 非易失性靜態(tài)RAM) |
| DS1267 | Dual Digital Potentiometer Chip(雙路數(shù)字電位器芯片) |
| DS1280 | 3-Wire to Bytewide Converter Chip(3線至字節(jié)寬度（8位）轉(zhuǎn)換芯片) |
| DS1284 | Watchdog Timekeeper Chip(看門狗計(jì)時(shí)器芯片) |
| DS1286 | Watchdog Timekeeper(看門狗計(jì)時(shí)器芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1249AB100 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB-100 | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1249AB-100# | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1249AB-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1249AB70 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
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