參數(shù)資料
型號: DS1249AB-70
廠商: DALLAS SEMICONDUCTOR
元件分類: Static RAM
英文描述: 256K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DIP32
封裝: 0.740 INCH, EXTENDED MODULE, DIP-32
文件頁數(shù): 2/8頁
文件大小: 140K
代理商: DS1249AB-70
DS1249Y/AB
2 of 8
READ MODE
The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs
(A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that
CE
and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for
CE
or tOE for OE rather than tACC.
WRITE MODE
The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1249Y provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1249AB and 4.5 volts for the
DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
相關PDF資料
PDF描述
DS1249AB-100 256K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DIP32
DS1249AB 256K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP32
DS1249Y 256K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP32
DS1249Y-70 256K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA32
DS1249Y-100 256K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA32
相關代理商/技術參數(shù)
參數(shù)描述
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DS1249AB-70IND 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
DS1249AB-70-IND 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based)
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DS1249AB-85 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube