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參數(shù)資料
| 型號： | DS1249AB-100 |
| 英文描述： | 2048k Nonvolatile SRAM |
| 中文描述： | 2048k非易失SRAM |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 153K |
| 代理商： | DS1249AB-100 |
DS1249Y/AB
7 of 8
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
slew from V
TP
to 0V
t
F
V
CC
slew from 0V to V
TP
t
R
V
CC
Valid to
CE
and
WE
Inactive
t
PU
V
CC
Valid to End of Write Protection
t
REC
(t
A
=25
°
C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
is measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1249 has a built-in switch that disconnects the lithium source until the user first applies V
CC
.
The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0
°
C to 70
°
C. For industrial products (IND), this range is -40
°
C to
+85
°
C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on V
CC
.
12. t
WR1
and t
DH1
are measured from
WE
going high.
13. t
WR2
and t
DH2
are measured from
CE
going high.
14. DS1249 modules are recognized by Underwriters Laboratory (U.L.
) under file E99151.
MIN
150
150
TYP
MAX
1.5
2
125
UNITS NOTES
μ
s
μ
s
μ
s
ms
ms
11
MIN
10
TYP
MAX
UNITS NOTES
years
9
相關PDF資料 |
PDF描述 |
|---|---|
| DS1249AB | 2048k Nonvolatile SRAM |
| DS1249AB100 | 2048k Nonvolatile SRAM |
| DS1249AB70 | 2048k Nonvolatile SRAM |
| DS1249Y | 2048k Nonvolatile SRAM |
| DS1249Y100 | 2048k Nonvolatile SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1249AB-100# | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1249AB-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1249AB70 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB-70 | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1249AB-70# | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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