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參數(shù)資料
| 型號： | DS1236A |
| 英文描述： | MicroManager Chip |
| 中文描述： | 微管理器芯片 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 320K |
| 代理商： | DS1236A |
DS1236A
11 of 20
the
NMI
output. In addition, as long as the IN pin is less than V
TP
, stimulation of the ST pin will result in
additional
NMI
pulses. In this way, the
ST
pin can be used to allow the CMOS processor to determine if
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in NO TAG. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 9, Figure 10, Figure 11, and
Figure 12. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 9 illustrates the relationship for power-down in CMOS mode. As V
CC
falls, the IN pin voltage drops below V
TP
. As a result, the processor is notified of an impending power
failure via an active
NMI
, which allows it to enter a sleep mode. As the power falls further, V
CC
crosses
V
CCTP
, the power monitor trip point. Since the DS1236A is in CMOS mode, no reset is generated. The
RST
voltage will follow V
CC
down, but will fall no further than V
BAT
. At this time,
CEO
is brought high
to write protect the RAM. When the V
CC
reaches V
BAT
, a power-fail is issued via the PF and
PF
pins.
Figure 10 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an
NMI
is issued. This gives the processor time to save critical data in nonvolatile SRAM. When V
CC
reaches V
CCTP
, an active RST and
RST
are given. The RST voltage will follow V
CC
as it falls.
CEO
, PF,
and
PF
will operate in a similar manner to CMOS mode. Notice that the
NMI
will tri-state to prevent a
loss of battery power.
Figure 11 shows the power-up sequence for the NMOS mode. As V
CC
slews above V
BAT
, the PF and
PF
pins are deactivated. An active reset occurs as well as an
NMI
. Although the
NMI
may be short due to
slew rates, reset will be maintained for the standard t
RST
timeout period. At a later time, if the IN pin falls
below V
TP
, a new
NMI
will occur. If the processor does not issue a
ST
, a watchdog reset will also occur.
The second
NMI
and RST are provided to illustrate these possibilities.
Figure 12 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236A
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
V
TP
. Depending on the processor type, the
NMI
may terminate the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/
SC
) allows the processor to disable all comparators on the DS1236A
before entering the Stop mode. This feature allows the DS1236A, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery-
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 13. The DS1236A may subsequently be restarted by a high-to-low
transition on the
PBRST
input through human interface via a keyboard, touchpad, etc. The processor will
then be restarted as the watchdog times out and drives RST and
RST
active. The DS1236A can also be
started up by forcing the WC/
SC
pin high from an external source. Also, if the DS1236A is placed in a
sleep mode by the processor and system power is lost, the DS1236A will wake up the next time V
CC
rises
above V
BAT
. These possibilities are illustrated in Figure 14.
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236A is
disabled, thus leaving the
NMI
, RST, and
RST
outputs disabled as well as the
ST
and IN inputs.
However, a loss of power during a sleep mode will result in an active RST and
RST
when the RC pin is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1238A | CAP 3.0UF 250VAC METALLIZED POLY |
| DS1245ABP-70-IND | GT 31C 1#4,2#8,14#12,14#16 SKT |
| DS1245ABP-85-IND | GT 24C 24#16 PIN PLUG |
| DS1245YP-100-IND | CAT5E PATCH CORD 10 FOOT BEIGE |
| DS1245YP-120-IND | CAT5E PATCH CORD 15 FOOT BEIGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1236A-10 | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| DS1236A-10+ | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| DS1236A-10N | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| DS1236A-10N+ | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| DS1236A-5 | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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