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參數(shù)資料
| 型號： | DS1212 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | 電源管理 |
| 英文描述： | Nonvolatile Controller x 16 Chip(非易失性控制器x 16 芯片) |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP28 |
| 封裝： | 0.600 INCH, DIP-28 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 77K |
| 代理商： | DS1212 |
DS1212
021798 2/6
OPERATION
The DS1212 performs six circuit functions required to
decode and battery back up a bank of up to 16 RAMs.
First, the 4 to 16 decoder provides selection of one of 16
RAMs. Second, a switch is provided to direct power
from the battery or V
CCI
supply, depending on which is
greater. This switch has a voltage drop of less than
0.2V. The third function the DS1212 provides is power
fail detection. It constantly monitors the V
CCI
supply.
When V
CCI
falls below 4.75 volts, or 4.5 volts, depend-
ing o n the level of tolerance Pin 3, a precision compara-
tor outputs a power fail detect signal to the decoder/chip
enable logic and the PF signal is driven low. The PF sig-
nal will remain low until V
CCI
is back in normal limits.
The fourth function of write protection is accomplished
by holding all chip enable outputs (CE0-CE15) to within
0.2 volts of V
CCI
or battery supply. If CE is low at the time
power fail detection occurs, the chip enable outputs are
kept in their present state until CE is driven high. The
delay of write protection until the current memory cycle
is completed prevents corruption of data. Power fail de-
tection occurs in the range of 4.75 volts to 4.5 volts with
tolerance Pin 3 grounded. If Pin 3 is connected to V
CCO
,
then power fail occurs in the range of 4.5 volts to 4.25
volts. During nominal supply conditions the chip enable
outputs follow the logic of a 4-to-16 decoder, shown in
Figure 1.
The fifth function the DS1212 performs is a battery sta-
tus warning so that data loss is avoided. Each time the
circuit is powered up, the battery voltage is checked with
a precision comparator. If the battery voltage is less
than 2 volts, the second memory cycle is inhibited. Bat-
tery status can, therefore, be determined by performing
a read cycle after power-up to any location in memory,
verifying that memory location content. A subsequent
write cycle can then be executed to the same memory
location, altering the data. If the next read cycle fails to
verify the written data, then the batteries are less than
2.0 volts and data is in danger of being corrupted.
The sixth function of the DS1212 provides for battery re-
dundancy. In many applications, data integrity is para-
mount. In these applications it is often desirable to use
two batteries to ensure reliability. The DS1212 provides
an internal isolation switch which allows the connection
of two batteries during battery backup operation. The
battery with the highest voltage is selected for use. If
one battery should fail, the other will then assume the
load. The switch to a redundant battery is transparent to
circuit operation and the user. A battery status warning
will only occur if both batteries are less than 2.0 volts.
For single battery applications the unused battery input
must be grounded.
NONVOLATILE CONTROLLER/DECODER
Figure 1
INPUTS
D
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
X
X
L
L
L
L
H
H
H
H
L
L
L
L
B
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
OUTPUTS
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
L
H
L
H
H
CE
CE0
CE1
CE2 CE3
CE4
CE5
CE6
CE7 CE8
CE9
CE10
CE11
CE12
CE13
CE14
CE15
PF
H = High Level
L = Low Level
X = Irrelevant
NOTE:
V
CCI
input is 250 mV lower when TOL PIN3 = V
CCO
.
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