- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376948 > DS1205S MultiKey Chip PDF資料下載
參數(shù)資料
| 型號： | DS1205S |
| 英文描述： | MultiKey Chip |
| 中文描述： | 多密鑰芯片 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 138K |
| 代理商： | DS1205S |
DS1205S
021798 12/17
4. The bus master writes a 0. This deselects ROM2
and ROM3 for the remainder of this search pass,
leaving only ROM1 and ROM4 connected to the
1-wire bus.
5. The bus master performs two more reads and re-
ceives a 0 bit followed by a 1 bit. This indicates that
all devices still coupled to the bus have 0’s as their
second ROM data bit.
6. The bus master then writes a 0 to keep both ROM1
and ROM4 coupled.
7. The bus master executes two reads and receives
two 0 bits. This indicates that both 1 bits and 0 bits
exist as the third bit of the ROM data of the attached
devices.
8. The bus master writes a 0 bit. This deselects ROM1
leaving ROM4 as the only device still connected.
9. The bus master reads the remainder of the ROM bits
for ROM4 and continues to access the part if de-
sired. This completes the first pass and uniquely
identifies one part on the 1-wire bus.
At this point, the bus master repeats the process de-
scribed above to determine the address of the remain-
ing devices on the 1-wire bus by repeating steps 1
though 7.
Note the following:
The bus master learns the unique ID number (ROM data
pattern) of one 1-wire device on each ROM Search op-
eration. The time required to derive the part’s unique ID
is:
960
μ
S + 3(8+64) X 0.06mS = 13.92mS
The bus master is therefore capable of identifying 60 dif-
ferent 1-wire devices per second.
Additionally, the data obtained from the two reads of
each set of three have the following interpretations:
00
-
There are still devices attached which have
conflicting bits in this position.
All devices still coupled have a zero bit in this bit
position.
All devices still coupled have a one bit in this bit
position.
There are no devices attached to the 1-wire
bus.
01
-
10
-
11
-
Transmitting/Receiving Data - All communications on
the 1-wire bus begin with the reset and presence detect
sequence. This sequence ensures the DS1205S is in
the listening mode. The bus master must then transmit
the 1-wire command to the DS1205S. To transmit the
first bit of the 1-wire I/O command, the master pulls the
bus low for 1
μ
S. This low-going edge informs the
DS1205S that the first bit is being sent. After 1
μ
S, the
master does one of two things:
1. holds the line low for an additional 70
μ
S to output a
0 (write a 0) or,
2. lets the bus go high for an additional 70
μ
S (write a 1).
The state of the bus during this 70
μ
S time phase deter-
mines the value of the bit. The DS1205S will sense any
rising edge during this 70
μ
S time phase as a one. After
the 70
μ
S has lapsed, the bus master must then drive
the bus high for 1
μ
S. This is the frame sync mentioned
earlier. This process is repeated until all the eight bits
are transmitted. Refer to the timing diagram in Figure
18.
The bus master now reads the family code identifier, fol-
lowed by the data and a CRC. The read cycle is similar
to the write cycle. It is started with the bus master pulling
the bus low for 1
μ
S. This informs the DS1205S that it
should have data on the bus no later than the 1
μ
S from
the falling edge. After the 1
μ
S, the bus master lets go of
the bus and the DS1205S drives the bus. The slave
must hold the data on the bus for an additional 14
μ
S
minimum (59
μ
S maximum). During the DS1205S hold-
ing time, the bus master reads the state of the bus. Ideal-
ly, the bus master should read data from the bus 15
μ
s
after the falling edge. The entire cycle time for one bit
lasts a minimum of 70
μ
S (140
μ
S maximum) from the
falling edge. At the end of the cycle, the bus master
drives the bus high for 1
μ
S. Again, this is like a frame
sync for the next bit. This read sequence is repeated un-
til all the data has been read. See the timing diagram in
Figure 19 for details. If for any reason the transaction
needs to be terminated before all the data is read, the
DS1205S must be reset.
CRC Generation - To validate the transmitted data from
the DS1205S, the bus master must generate a CRC val-
ue for the data as it is received. This generated value is
compared to the value stored in the last eight bits of the
DS1205S. The bus master computes the CRC over the
8-bit family code and all 48 ID number data bits, but NOT
over the stored CRC value itself. The CRC is calculated
using the following polynomial.
CRC = px
3
+ px
2
+ 1
If the two CRC values match, the transmission is error-
free.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1205V | MultiKey |
| DS1208 | dallas semiconductor reliability report |
| DS1210 | Nonvolatile Controller Chip |
| DS1211 | Nonvolatile Controller x 8 Chip |
| DS1217M | Nonvolatile Read/Write Cartridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1205V | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:MultiKey |
| DS1206N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface |
| DS1206S | 制造商:Maxim Integrated Products 功能描述: |
| DS1206SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface |
| DS1207 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|MODULE|5PIN|PLASTIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。