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參數(shù)資料
| 型號(hào)： | DS1100LC-301+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 5TAP 301NS 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 標(biāo)片/步級(jí)數(shù)： | 5 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 60.2ns |
| 接頭增量： | 60.2ns |
| 可用的總延遲： | 301ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1100L
4 of 7
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:
Ambient Temperature:
25°C
±3°C
Supply Voltage (VCC):
3.3V
±0.1V
Input Pulse:
High = 3.0V
±0.1V
Low = 0.0V
±0.1V
Source Impedance:
50
max
Rise and Fall Time:
3.0ns max (measured between 10% and 90%)
Pulse Width:
500ns (1μs for -500 version)
Period:
1μs (2μs for -500 version)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
Note: Above conditions are for test only and do not restrict the operation of the device under other
data sheet conditions.
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