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參數(shù)資料
| 型號： | DS1100LC-301+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 5TAP 301NS 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 標片/步級數(shù)： | 5 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 60.2ns |
| 接頭增量： | 60.2ns |
| 可用的總延遲： | 301ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1100L
3 of 7
CAPACITANCE
(TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and
trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature
range, and a supply-voltage range of 3.0V to 3.6V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1
slows down, all other taps also slow down; TAP 3 can never be faster than TAP 2.
4) Intermediate delay values are available on a custom basis. For further information, contact the factory at
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
10) The “-75” version is specified and tested with an additional 2ns of tolerance on the specified minimum
input-to-tap delay tolerance parameter for TAP 1. Delay values for TAP 2 to TAP 5 meet data sheet
specifications.
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
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