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參數(shù)資料
| 型號： | DS1023S-50/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 標(biāo)片/步級數(shù)： | 256 |
| 功能： | 單發(fā)射，可編程 |
| 延遲到第一抽頭： | 16.5ns |
| 接頭增量： | 0.5ns |
| 可用的總延遲： | 127.5ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1023
13 of 16
NOTES:
1. Delay from input to output with a programmed delay value of zero.
2. This is the relative delay between REF and OUT. The device is trimmed such that when programmed
to zero delay the OUT output will always appear before the REF output. This parameter is
numerically equal to tD0-tREF. (See Figure 15).
3. The reference delay is closely matched to the step zero delay to allow relative timings down to zero or
less.
4. This is the worst case condition when the SubDAC switches from its maximum to minimum value.
All other steps are
±0.5 lsb. This comment does not apply to -200 and -500 devices which do not use
a SubDAC. (See Figure 14)
5. This is the actual measured delay from IN to OUT. This parameter will exhibit greater temperature
variation than the relative delay parameter.
6. This is the actual measured delay with respect to the REF output. This parameter more closely
reflects the programmed delay value than the absolute delay parameter. (See Figure 15).
7. This is the maximum deviation from a straight line response drawn between the step zero delay and
the maximum programmed delay. Therefore it is indicative of the maximum error in the measured
delay versus the programmed delay with respect to the REF output. The absolute delay measurement
from IN to OUT will in addition have an offset error equal to the step zero delay and its tolerance.
(See Figure 13).
8. Change in delay value when the inverted output is selected instead of the normal, non-inverting,
output.
9. In PWM mode the delay between the rising edge of the input and the rising edge of the output.
10. The minimum value for which the PWM pulse width should be programmed. Narrower pulse widths
may be programmed but output levels may be impaired and ultimately no output pulse will be
produced.
11. This is the minimum allowable interval between transitions on the input to assure accurate device
operation. This parameter may be violated but timing accuracy may be impaired and ultimately very
narrow pulse widths will result in no output from the device.
12. This parameter applies to normal delay mode only. When a 50% duty cycle input clock is used this
defines the highest usable clock frequency. When asymmetrical clock inputs are used the maximum
usable clock frequency must be reduced to conform to the minimum input pulse width requirement. In
PWM mode the minimum input period is equal to the step zero delay and the programmed delay
(tDO + tD).
13. Measured from rising edge of the input to the rising edge of the output (tDR).
14. From rising edge to rising edge.
15. Faster rise and fall times will give the greatest accuracy in measured delay. Slow edges (outside the
specification maximum) may result in erratic operations.
16. Min and max limits do not apply for steps 253-255. Only the typical value applies for those steps.
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