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參數(shù)資料
| 型號： | DRV591GQE |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 256K |
| 代理商： | DRV591GQE |
DRV591
SLOS389
–
NOVEMBER 2001
13
www.ti.com
APPLICATION INFORMATION
LC filter in the time domain (continued)
For L = 10
μ
H and C = 10
μ
F, the cutoff frequency, f
o
, is 15.9 kHz. For worst case duty cycle of 0.5 and
V
TEC
=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the
ripple voltage by the TEC resistance of 1.5
, resulting in a ripple current through the TEC element of 4.1 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 22
μ
F) with relatively high ESR (greater than 100 m
), such as electrolytic
capacitors, the ESR dominates over the charging-discharging of the capacitor. The following simple
equation (6) may be used to estimate the ripple voltage:
VC
IL
IL
RESR
inductor ripple current
RESR
filter capacitor ESR
For a 100
μ
F electrolytic capacitor, an ESR of 0.1
is common. If the 10
μ
H inductor is used, delivering 250 mA
of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times
that of the 10
μ
F ceramic capacitor, as ceramic capacitors typically have negligible ESR.
For worst case conditions, the on-resistance of the output transistors has been ignored to give the maximum
theoretical ripple current. In reality, the voltage drop across the output transistors decreases the maximum V
O
as the output current increases. It can be shown using equation (4) that this decreases the inductor ripple
current, and therefore the TEC ripple current.
switching frequency configuration: oscillator components R
OSC
and C
OSC
and FREQ operation
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The
frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ
pin either low (500 kHz) or high (100 kHz). Table 1 shows the values required and FREQ pin configuration for
each switching frequency.
Table 1. Frequency Configuration Options
SWITCHING FREQUENCY
ROSC
120 k
120 k
COSC
220 pF
FREQ
500 kHz
LOW (GND)
100 kHz
1 nF
HIGH (VDD)
For proper operation, the resistor R
OSC
should have 1% tolerance while capacitor C
OSC
should be a ceramic
type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND
at a single point, typically where power and ground are physically connected to the printed-circuit board.
external clocking operation
To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal
into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage
requirements specified in the electrical specifications table. Since the DRV591 includes an internal frequency
doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock frequency
are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC to ground
may be omitted from the circuit in this mode of operation
—
the source is disconnected internally.
(6)
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| DRV591VFPG4 | 功能描述:功率驅(qū)動器IC High Efficiency PWM Power Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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