參數(shù)資料
型號(hào): DRV101T
英文描述: PWM SOLENOID/VALVE DRIVER
中文描述: 脈寬調(diào)制電磁/閥驅(qū)動(dòng)
文件頁數(shù): 10/19頁
文件大?。?/td> 298K
代理商: DRV101T
10
DRV101
Voltage Controlled Duty Cycle
Duty cycle can also be programmed with an analog voltage,
V
PWM
. With V
PWM
0.75V, duty cycle is near 90%. Increas-
ing this voltage results in decreased duty cycles. Table II
provides V
PWM
values for typical duty cycles. See the “Duty
Cycle vs Voltage” Typical Performance Curve for addi-
tional duty cycles.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 4) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
FIGURE 5. Simplified Circuit Model of the Duty Cycle
Adjust Pin.
STATUS FLAG
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a
fault condition, Flag output is driven low (pin voltage
typically drops to 0.3V). A pull-up resistor, as shown in
Figure 6, is required to interface with standard logic. A small
value capacitor may be needed between Flag and ground in
noisy applications.
Figure 6 gives an example of a non-latching fault monitoring
circuit, while Figure 7 provides a latching version. The Flag
pin can sink several milliamps, sufficent to drive external
logic circuitry or an LED (Figure 8) to indicate when a fault
has occurred. In addition, the Flag pin can be used to turn off
other DRV101’s in a system for chain fault protection.
The DRV101’s internal 24kHz oscillator sets the PWM
period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200
μ
A current
source and connects to the input of a comparator and a 19k
resistor as shown in Figure 5. The DRV101’s PWM control
design is inherently monotonic. That is, a decreased voltage
(or resistor value) always produces an increased duty cycle.
200μA
3
V
S
Comparator
Duty Cycle
Adjust
DRV101
19k
Resistor or
Voltage Source
(1)
NOTE: (1) Do not drive pin below 0.1V.
3.8V
0.7V
f = 24kHz
FIGURE 4. Using a Voltage to Program Duty Cycle.
DRV101
D/A
Converter
(or analog
voltage)
1k
(1)
PWM
V
PWM
V
S
3
4
6
5
Out
NOTE: (1) Required if voltage source can go below 0.1V.
DRV101
Thermal Shutdown
Over/Under Current
4
6
7
Out
5k
Pull-Up
+5V
Flag
TTL or HCT
FIGURE 7. Latching Fault Monitoring Circuit.
FIGURE 6. Non-Latching Fault Monitoring Circuit.
DRV101
Thermal Shutdown
Over/Under Current
4
6
7
Out
20k
+5V
Flag
Q
Q
CLR
Flag
Flag
Flag Reset
J
CLK
GND
K
V
S
74XX76A
(1)
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
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