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參數(shù)資料
| 型號： | DPS256X32V3-85M |
| 廠商： | TWILIGHT TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 32 MULTI DEVICE SRAM MODULE, 85 ns, CPGA66 |
| 封裝： | 1.090 X 1.090 INCH, 0.400 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 695K |
| 代理商： | DPS256X32V3-85M |
DPS256X32V3
Dense-Pac Microsystems, Inc.
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V
at DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of
±500mV from steady
state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are
in the output state, and input signals of opposite phase to
the outputs must not be applied.
7. The outputs are in a high impedance state when WE is
LOW.
8. SEL controls address buffer, WE buffer, CE buffer and OE
buffer and DIN buffer. If SEL controls Data Retention Mode,
VIN levels (Address, WE, OE, CE, I/O) can be in the high
impedance state. If CE controls Data Retention Mode, SEL
must be SEL
≥ VDD -0.2V or 0V ≤ SEL ≤ 0.2V. The other
input levels (Address, WE, OE, I/O) can be in the high
impedance state.
9. tCW is measured from the later of CE going Low or SEL going
HIGH to the End of Write.
10. tAS is measured from the Address Valid to the beginning of
Write.
11. A Write occurs during the overlap of a LOW CE, a HIGH
SEL and a LOW WE. A Write begins at the latest transition
among CE going LOW, SEL going HIGH and WE going
LOW. A Write ends at the earliest transition among CE
going HIGH, SEL going LOW and WE going HIGH. tWP is
measured from the beginning of Write to the end of Write.
12. tWR is measured from the earliest of CE or WE going HIGH
or SEL going LOW to the end of Write Cycle.
13. If CE goes LOW simultaneously with WE going LOW or
after WE going LOW, the outputs remain in high impedance
state.
14. DOUT is the same phase of the last written data in this Write
Cycle.
15. DOUT is the Read data of next Address.
16. If CE is LOW and SEL is high during this period, I/O pins are
in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied.
WRITE CYCLE 2: CE Controlled. OE is LOW. 13, 14, 15, 16
ADDRESS
CE
SEL
WE
DATA OUT
DATA IN
30A044-00
REV. E
6
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