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參數(shù)資料
| 型號(hào)： | DPS256X32V3-85M |
| 廠商： | TWILIGHT TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 32 MULTI DEVICE SRAM MODULE, 85 ns, CPGA66 |
| 封裝： | 1.090 X 1.090 INCH, 0.400 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 695K |
| 代理商： | DPS256X32V3-85M |
8 Megabit CMOS SRAM
DPS256X32V3
DESCRIPTION:
The DPS256X32V3 ‘’VERSA-STACK’’ module is a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers
(SLCC) mounted on a co-fired ceramic substrate. It offers 8
Megabits of SRAM in a package envelope of 1.09 x 1.09 x 0.40
inches.
The DPS256X32V3 contains eight individual 128K x 8
SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a
higher board density of memory than available with
conventional through-hole, surface mount, module, or most
hybrid techniques.
FEATURES:
Organizations Available:
256K x 32, 512K x 16,
or 1024K x 8
Access Times:
70*, 85, 100, 120, 150ns
Fully Static Operation -
No clock or refresh required
Single +5V Power Supply,
±10% Tolerance
TTL Compatible
Common Data Inputs
and Outputs
Low Data Retention Voltage:
2.0V min.
66-Pin PGA
‘’VERSA-STACK’’ Package
* Commercial only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O31
Data Input/Output
CE0 - CE7
Low Chip Enables
SEL0, SEL1
High Chip Enables
WE0, WE1
Write Enables
OE
Output Enable
VDD
Power (+5V)
VSS
Ground
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A044-00
REV. E
1
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