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參數(shù)資料
| 型號： | DP83848CVV/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 9/86頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 48-LQFP |
| 產(chǎn)品培訓模塊： | PHYTER® Family |
| 標準包裝： | 250 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1276 (CN2011-ZH PDF) |
| 配用： | DP83848C-POE-EK-ND - BOARD EVALUATION DP83848C DP83848C-MAU-EK-ND - BOARD EVALUATION DP83848C |
| 其它名稱： | *DP83848CVV *DP83848CVV/NOPB DP83848CVV DP83848CVVNOPB DP83848CVVNOPB-ND DP83848CVVNOPBTR DP83848CVVNOPBTR-ND |
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DP
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8C
2.0 Configuration
This section includes information on the various configura-
tion options available with the DP83848C. The configura-
tion options described below include:
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
—BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest per-
formance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83848C supports four differ-
ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the high-
est performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83848C can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
2.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the
DP83848C is forced into a specific mode or Auto-Negotia-
tion will advertise a specific ability (or set of abilities) as
given in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 0x00h.
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848C trans-
mits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-
Duplex, and Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis-
abled, the Speed Selection bit in the BMCR controls
switching between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of oper-
ation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is
achieved.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83848C (only the 100BASE-T4 bit is not set since the
DP83848C does not support that function).
The BMSR also provides status on:
— Whether or not Auto-Negotiation is complete
— Whether or not the Link Partner is advertising that a re-
mote fault has occurred
— Whether or not valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR)
indicates the Auto-Negotiation abilities to be advertised by
the DP83848C. All available abilities are transmitted by
default, but any ability can be suppressed by writing to the
Table 1. Auto-Negotiation Modes
AN_EN
AN1
AN0
Forced Mode
0
10BASE-T, Half-Duplex
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-TX, Half-Duplex
0
1
100BASE-TX, Full-Duplex
AN_EN
AN1
AN0
Advertised Mode
1
0
10BASE-T, Half/Full-Duplex
1
0
1
100BASE-TX, Half/Full-Duplex
1
0
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DP83848CVVX | 制造商:Texas Instruments 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP T/R |
| DP83848CVVX/NOPB | 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848EVV/NOPB | 功能描述:以太網(wǎng) IC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848EVVX/NOPB | 功能描述:以太網(wǎng) IC 10/100 ETHERNET PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848H | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DP83848H PHYTER㈢ Mini - Extreme Single 10/100 Ethernet |
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