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| 型號： | DO-DI-PCIX64-VE |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DO-DI-PCIX64-VE |
LogiCORE PCI Interface v3.0
DS 208 (v.1.2) June 28, 2002
Data Sheet, v3.0.99
www.xilinx.com
1-800-255-7778
5
Recommended Design Experience
The LogiCORE PCI-X Interface is pre-implemented allow-
ing engineering focus on the unique user application func-
tions
of
a
PCI-X
design.
high-performance design that is challenging to implement in
any technology. Therefore, previous experience with build-
ing high-performance, pipelined FPGA designs using Xilinx
implementation software, constraint files, and guide files is
recommended. The challenge to implement a complete
PCI-X design including user application functions varies
depending on configuration and functionality of your appli-
cation. Contact your local Xilinx representative for a closer
review and estimation for your specific requirements.
Regardless,
PCI-X
is
a
Timing Specifications
The maximum speed at which your user design is capable
of running can be affected by the size and quality of the
design. The following tables show the key timing parame-
ters for the LogiCORE PCI-X Interface. Timing Parameters
in the 66MHz PCI-x are listed in
Table 4
. Timing Parameters
in the 33MHz PCI are listed in
Table 5
.
Ordering Information
This core may be downloaded from the Xilinx
forAlliance and Foundation Series Software packages, at no
additional charge.
Part Numbers
DO-DI-PCIX64-VE
-PCI-X 64-bit 66/100 MHz IP only Core
DX-DI-64IP-XVE
- Upgrade from
DO-DI-PCI64/DO-DI-PCI-AL/DO-DI-PCI64DK to
DO-DI-PCIX64-VE
To order Xilinx’s PCI Core, please visit the Xilinx
Silicon
Xpresso Cafe
or contact your local Xilinx
sales representa-
tive
.
Information on additional Xilinx LogiCORE modules is avail-
able on the Xilinx
IP Center
.
Table 4:
Timing Parameters, 66MHz PCI-X
Table 5:
Timing Parameters, 33MHz PCI
Revision History
The following table shows the revision history for this document.
Symbol
T
cyc
T
high
T
low
T
val
Parameter
Min
15
1
6
6
0.7
2
Max
20
-
-
3.8
2
CLK Cycle Time
CLK High Time
CLK Low Time
CLK to Signal Valid Delay
(bussed signals)
CLK to Signal Valid Delay
(point to point signals)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
(bussed signals)
Input Setup Time to CLK
(point to point signals)
Input Hold Time from CLK
Reset Active to Output Float
T
val
0.7
2
3.8
2
T
on
T
off
T
su
0
2
-
1.7
2
-
7
2
-
T
su
1.7
2
-
T
h
0.5
2
-
-
T
rstoff
40
Notes:
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCIX.
3. Operation at 100 MHz requires T
su
of 1.2 and T
cyc
of 10.
Symbol
T
cyc
T
high
T
low
T
val
Parameter
Min
30
1
11
11
2
2
Max
-
-
-
11
2
CLK Cycle Time
CLK High Time
CLK Low Time
CLK to Signal Valid Delay
(bussed signals)
CLK to Signal Valid Delay
(point to point signals)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
(bussed signals)
Input Setup Time to CLK
(point to point signals)
Input Hold Time from CLK
Reset Active to Output Float
T
val
2
2
11
2
T
on
T
off
T
su
2
2
-
7
2
-
28
1
-
T
su
10
2
-
T
h
0
2
-
-
T
rstoff
40
Notes:
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCI33_3 or PCIX.
Date
Version
Revision
06/28/02
1.0
New template
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