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| 型號(hào)： | DO-DI-PCI32-IP |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項(xiàng) |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大小： | 150K |
| 代理商： | DO-DI-PCI32-IP |
LogiCORE PCI32 Interface v3.0
2
1-800-255-7778Data Sheet, v3.0.100Applications
Embedded applications in networking, industrial,
and telecommunication systems
PCI add-in boards such as frame buffers, network
adapters, and data acquisition boards
Hot swap CompactPCI boards
CardBus compliant
Any applications that need a PCI interface
General Description
The LogiCORE PCI Interface is a preimplemented and fully
tested module for Xilinx FPGAs. The pinout for each device
and the relative placement of the internal logic are pre-
defined. Critical paths are controlled by constraint and guide
files to ensure predictable timing. This significantly reduces
the engineering time required to implement the PCI portion
of your design. Resources can instead be focused on your
unique user application logic in the FPGA and on the sys-
tem-level design. As a result, LogiCORE PCI products min-
imize your product development time.
The core meets the setup, hold, and clock-to-timing require-
ments as specified in the PCI-X specification. The interface
is verified through extensive simulation.
Other features that enable efficient implementation of a PCI
system include:
Block
SelectRAM
memory.
Blocks
of
on-chip
ultra-fast RAM with synchronous write and dual-port
RAM capabilities. Used in PCI designs to implement
FIFOs.
SelectRAM memory. Distributed on-chip ultra-fast RAM
with synchronous write option and dual-port RAM
capabilities. Used in PCI designs to implement FIFOs.
Internal three-state bus capability for data multiplexing.
The interface is carefully optimized for best possible perfor-
mance and utilization in Xilinx FPGA devices.
Smart-IP Technology
Drawing on the architectural advantages of Xilinx FPGAs,
Xilinx Smart-IP technology ensures the highest perfor-
mance, predictability, repeatability, and flexibility in PCI
designs. The Smart-IP technology is incorporated in every
LogiCORE PCI interface.
Xilinx Smart-IP technology leverages the Xilinx architectural
advantages, such as look-up tables and segmented routing,
as well as floorplanning information, such as logic mapping
and location constraints. This technology provides the best
physical layout, predictability, and performance. In addition,
these features allow for significantly reduced compile times
over competing architectures.
To guarantee the critical setup, hold, minimum clock-to-out,
and maximum clock-to-out timing, the PCI interface is deliv-
ered with Smart-IP constraint files that are unique for a
device and package combination. These constraint files
guide the implementation tools so that the critical paths
always are within specification.
Xilinx provides Smart-IP constraint files for many device
and package combinations. Constraint files for unsupported
device and package combinations may be generated using
the web-based constraint file generator.
Functional Description
The LogiCORE PCI Interface is partitioned into five major
blocks and a user application as shown in
Figure 1
.
LogiCORE Facts (Cont)
Supported Devices
Virtex V200FG256-6C
Virtex-E V200EFG256-6C
Virtex-E V400EFG676-6C
Virtex V300BG432-5C
Virtex V1000FG680-5C
Virtex-E V100EBG352-6C
Virtex-E V300EBG432-6C
Virtex-E V1000EFG680-6C
Virtex-II 2V1000FG456-4C/I/M
Virtex-II Pro 2VP7FF672-6C
Spartan-II 2S30PQ208-5C
Spartan-II 2S50PQ208-5C
Spartan-II 2S100PQ208-5C
Spartan-II 2S150PQ208-5C
Spartan-II 2S200PQ208-5C
Spartan-IIE 2S50EPQ208-6C
Spartan-IIE 2S100EPQ208-6C
Spartan-IIE 2S150EPQ208-6C
Spartan-IIE 2S200EPQ208-6C
Spartan-IIE 2S300EPQ208-6C
PCI32/66
3.3v only
3.3v only
3.3v only
3.3v, 5.0v
3.3v, 5.0v
3.3v only
3.3v only
3.3v only
3.3v only
3.3v only
3.3v, 5.0v
3.3v, 5.0v
3.3v, 5.0v
3.3v, 5.0v
3.3v, 5.0v
3.3v only
3.3v only
3.3v only
3.3v only
3.3v only
PCI32/33
Xilinx provides technical support for this LogiCORE product when used as described
in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing,
functionality, or support of product if implemented in devices not listed, or if custom-
ized beyond that allowed in the product documentation.
Note: Universal card implementations require two bitstreams.
Note: Virtex-E and Spartan-IIE recommended for CardBus.
Note: Commercial devices; 0 C < T
< 85 C.
Note: For additional Part/Package combinations, see the UCF Generator in the PCI
Lounge.
Note: 2V1000 is supported over Military Temp. range.
Figure 1:
LogiCORE PCI Interface Block Diagram
Parity
Generator/
Checker
PCI Configuration Space
Initiator
MState
Interrupt
PLine
Register
Latency
Timer
Register
Vendor ID,
OtRev ID,
Data
Target
State
Machine
P
U
ADIO[63:0]
AD[63:0]
PAR
GNT-
PERR-
SERR-
FRAME-
IRDY-
REQ-
TRDY-
DEVSEL-
STOP-
Base
Address
Register
0
Base
Address
Register
1
Command/
Status
Register
Base
Address
Register
2
REQ64-
ACK64-
PAR64
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