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參數(shù)資料
| 型號： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 6/61頁 |
| 文件大小： | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
6
Preliminary
Version: DM9801-DS-P02
March 20, 2000
Pin Description
(Continued)
PHY Address Interface:
PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a
PHY isolation condition. See the isolate bit description in the BMCR, address 00.
68
PHYADSEL
(PHYAD0)
Or
SCLK
CONFIG1 and CONFIG0 are not set to 1.
0 = 0x01 address
1 = 0x1F address
PHY Address 0 (MII Mode, INTFSEL = 0):
PHY address bit 0 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1.
Serial Interface Clock (GPSI Mode, INTFSEL = 1):
SCLK is a bi-directional clock signal used to synchronize SI, SO and SCS#
to and from the DM9801 SPI bus.
8
Z
PHY address bit 1 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
9
Z
PHY address bit 2 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
10
Z
PHY address bit 3 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
47
Z
PHY address bit 4 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
I/O,Z
MII Serial Management PHY Address Select (MII Mode, INTFSEL = 0):
PHYADSEL is an input signal that selects one of two PHY addresses within
the 32 address range for the DM9801 MII management interface when both
PHYAD1
I/O,
PHY Address 1 (MII Mode, INTFSEL = 0):
PHYAD2
I/O,
PHY Address 2 (MII Mode, INTFSEL = 0):
PHYAD3
I/O,
PHY Address 3 (MII Mode, INTFSEL = 0):
PHYAD4
I/O,
PHY Address 4 (MII Mode, INTFSEL = 0):
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