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參數(shù)資料
| 型號： | DM9601E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB Ethernet MAC Controller with Intergrated 10/100 PHY |
| 中文描述： | USB以太網(wǎng)MAC控制器與集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 31/58頁 |
| 文件大小： | 603K |
| 代理商： | DM9601E |
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DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary
Version: DM9601-DS-P01
June 22, 2001
31
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in 10Mbps
mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
1.1
Jabber detect
0,RO/LH
1.0
Extended
capability
1,RO/P
11.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9601. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
2.15-2.0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores that bit 3 to 18 of the OUI (00606E) are
mapped to bit 15 to 0 of this register respectively. The most
significant two bits of the OUI are ignored (the IEEE standard refers
to these as bit 1 and 2)
11.4 PHY Identifier Register #2 (PHYID2) - 03
Bit
Bit Name
Default
Description
3.15-3.10
OUI_LSB
<101110>,
RO/P
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
3.9-3.4
VNDR_MDL
<001000>,
RO/P
3.3-3.0
MDL_REV
<0000>,
RO/P
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相關(guān)代理商/技術(shù)參數(shù) |
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