參數(shù)資料
型號(hào)： DM9601E
廠商： Electronic Theatre Controls, Inc.
英文描述： USB Ethernet MAC Controller with Intergrated 10/100 PHY
中文描述： USB以太網(wǎng)MAC控制器與集成10/100網(wǎng)卡芯片
文件頁(yè)數(shù)： 23/58頁(yè)
文件大?。?/td> 603K
代理商： DM9601E
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9601-DS-F01
June 22, 2002
23
10.11 RX/TX Flow Control Register ( 0AH )
Bit
7
Name
TXP0
Default
0,RW
Description
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = 0000H
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = FFFFH.
Force TX Pause Packet Enable
Enable the pause packet for high/low water threshold control.
Back pressure mode. This mode is for half duplex mode only. Generates a jam
pattern when any packet coming and RX SRAM over BPHW.
Back pressure mode. This mode is for half duplex mode only. Generates a jam
pattern when a packet’s DA match and RX SRAM over BPHW.
RX pause packet status, latch and read clear
RX pause packet current status
Flow Control Enable
Set to enable the flow control mode(i.e. to disable TX function).
6
TXPF
0,RW
5
TXPEN
0,RW
4
BKPA
0,RW
3
BKPM
0,RW
2
1
0
RXPS
RXPCS
FLCE
0,R/C
0,RO
0,RW
10.12 EEPROM & PHY Control Register ( 0BH )
Bit
7:6
5
4
3
Name
Default
0,RO
0,RW
0,RW
0,RW
Description
RESERVED
REEP
WEP
EPOS
Reserved
Reload EEPROM. Driver needs to clear it after operation complete.
Write EEPROM enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY.
EEPROM Read or PHY Register Read Command. Driver needs to clear it after
operation complete.
EEPROM Write or PHY Register Write Command. Driver needs to clear it after
operation complete.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress.
2
ERPRR
0,RW
1
ERPRW
0,RW
0
ERRE
0,RO
10.13 EEPROM & PHY Address Register ( 0CH )
Bit
7:6
Name
PHY_ADR
Default
1,RW
Description
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
EEPROM Word Address or PHY Register Address
5:0
EROA
0,RW
10.14 EEPROM & PHY Data Register ( EE_PHY_L
：
0DH EE_PHY_H
：
0EH )
Bit
7:0
7:0
Name
EE_PHY_L
EE_PHY_H
Default
X,RW
X,RW
Description
EEPROM or PHY Low Byte Data
EEPROM or PHY High Byte Data
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