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參數(shù)資料
| 型號(hào)： | DM9161 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 8/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161 |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8
Final
Version: DM9161-DS-F02
May 10,2002
5.2 Media Interface, 4 pins
Pin No.
3,4
Pin Name
RX+
RX-
TX+
TX-
I/O
I
Description
Differential Receive Pair
Differential data is received from the media
Differential Transmit Pair/PECL Transmit Pair
Differential data is transmitted to the media in TP mode
7,8
O
5.3 LED Interface, 3 pins
Pin No.
11
Pin Name
FDX
/COL LED#
/OP0
I/O
O,
LI
(U)
Description
Full/Half Duplex LED
Active states indicate the full-duplex mode. Active states see LED
configuration
Full-Duplex/Collision LED: when bit 5 of register 16 is set high
Active states indicate the full-duplex mode or activity Collision LED when
in the half-duplex mode. Active states see LED configuration
OP0: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161 according to the Table A. The value is latched into the DM9161
registers at power-up/reset
Speed LED
Active states indicate the 100Mbps mode. Active states see LED
configuration
When bit 6 of Register 16 is set high, it controls the SPEED LED as
100Base-TX SD signal output. For debug only
OP1: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161 according to the Table A. The value is latched into the DM9161
registers at power-up/reset
Link LED & Activity LED:
Active states indicate the good link for 10Mbps and 100Mbps operations.
It is also an active LED function when transmitting or receiving data.
Active states see LED configuration
OP2: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161 according to the Table A. The value is latched into the DM9161
registers at power-up/reset
12
SPEED LED#
/OP1
O,
LI
(U)
13
LINK /ACT
LED#
/OP2
O,
LI
(U)
5.4 Mode, 2 pins
Pin No.
10
Pin Name
PWRDWN
I/O
I
Description
Power Down Control
Asserted high to force the DM9161 into power down mode. When in
power down mode, most of the DM9161 circuit block’s power is turned
off, only the MII management interface (MDC, MDIO) logic is available
(the PHY should respond to management transactions and should not
generate spurious signals on the MII)). To leave power down mode, the
DM9161 needs the hardware or software reset with the PWRDWN pin
low
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9161E | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9301F | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9324 | 5-Bit Comparator |
| DM9324N | 5-Bit Comparator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161_08 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver |
| DM9161A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161A_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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