參數(shù)資料
型號(hào)： DM9161
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述： 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁(yè)數(shù)： 29/47頁(yè)
文件大?。?/td> 561K
代理商： DM9161
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 29
Version: DM9161-DS-F02
May 10,2002
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
17.15
Bit Name
100FDX
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-
17.9
17.8-17.4
Reserved
0, RO
PHYADR[4:0]
(PHYADR),
RW
17.3-17.0
ANMB[3:0]
0, RO
B3 b2 b1 B0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
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