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參數(shù)資料
| 型號： | DM74S112 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs(帶清零和互補輸出的雙負(fù)邊緣觸發(fā)的主-從J-K觸發(fā)器) |
| 中文描述： | S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 43K |
| 代理商： | DM74S112 |
2000 Fairchild Semiconductor Corporation
DS006459
www.fairchildsemi.com
August 1986
Revised April 2000
D
O
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↓
=
Negative going edge of pulse.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
*
=
This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Order Number
DM74S112
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
H
H
H
H
CLR
H
L
L
H
H
H
H
CLK
X
X
X
↓
↓
↓
↓
H
J
X
X
X
L
H
L
H
K
X
X
X
L
L
H
H
Q
H
L
H*
Q
0
H
L
Q
L
H
H*
Q
0
L
H
Toggle
H
H
X
X
Q
0
Q
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74S112 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74S112J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM74S112N | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74S11J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM74S11N | 功能描述:邏輯門 Trp 3-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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