Table 2 Instruction Functions
No. 4433-10/11
DM2023
Code
Execution time
(when f
OSC
= 250 kHz)
82 μs to 1.64 ms
Instruction
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description
Display clear
0
0
0
0
0
0
0
0
0
1
Clears the whole display and then returns
the cursor to the home position (location 0).
Cursor home
0
0
0
0
0
0
0
0
1
*
Returns the cursor to the home position.
Also restores a shifted display. The
contents of DD RAM are not changed.
40 μs to 1.6 ms
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
Sets the cursor advance position and
whether the display shifts. These operations
are performed when data is read or written.
40 μs
Display on/off
control
0
0
0
0
0
0
1
D
C
B
Sets the display on/off state (D), the cursor
on/off state (C), and the blinking state (B)
of the character at the cursor position.
40 μs
Cursor/display shift
0
0
0
0
0
1
S/C
R/L
*
*
Performs cursor motion and display shift
without changing the contents of DD RAM.
40 μs
Function set
0
0
0
0
1
DL
N
F
*
*
Sets the interface data length (DL), the
number of display lines (N), and the
character font (F).
40 μs
CG RAM address
set
0
0
0
1
ACG
Sets the CG RAM address. The next data
transmitted will be CG RAM data.
40 μs
DD RAM address
set
0
0
1
ADD
Sets the DD RAM address. The next data
transmitted will be DD RAM data.
40 μs
Busy flag/address
readout
0
1
BF
AC
Reads out the busy flag (BF), which
indicates the internal operation in progress
state, and the contents of the address
register.
1 μs
CG RAM/DD RAM
data write
1
0
Write data
Writes to DD RAM or CG RAM.
40 μs
CG RAM/DD RAM
data read
1
1
Read data
Reads data from DD RAM or CG RAM.
40 μs
I/D = 1: Increment (+1)
I/D = 0: Decrement (–1)
S = 1:
Display shift at the same time
S/C = 1: Display shift
S/C = 0: Cursor move
R/L = 1: Right shift
R/L = 0: Left shift
DL = 1: 8 bits, DL = 0: 4 bits
N = 1:
2 lines, N = 0: 1 line
F = 1:
5
×
10 dots, F = 0: 5
×
7 dots
BF = 1: Internal operation in progress
BF = 0: Instructions accepted
*
: Invalid (don’t care)
DD RAM: Display data RAM
CG RAM: Character generator RAM
ACG:
A CG RAM address
ADD:
Corresponds to a DD RAM
address
AC:
The address counter, which is
used for both DD and CG RAMs.
The execution times
will change if the
internal oscillator
frequency is
changed.
Example: If an f
OSC
of 270 kHz is used,
then a 40 μs time
from this chart will
become 40 μs
×
250/270 = 37 μs.