參數(shù)資料
型號(hào)： DM1M32SJ6-10
英文描述： Enhanced DRAM (EDRAM) Module
中文描述： 增強(qiáng)的DRAM（eDRAM內(nèi)存）模塊
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 124K
代理商： DM1M32SJ6-10
2-38
initiating the write cycle wth the falling edge of /RE). The write
address and data can be latched very quickly after the fall of /RE
(t
RAH
+ t
ASC
for the column address and t
DS
for the data). During a
write burst sequence, the second write data can be posted at time
t
RSW
after /RE. Subsequent writes wthin a page can occur wth write
cycle time t
PC
. Wth /Genabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify or randomread-write
sequences wthin the page wth 12ns cycle times. During a write hit
sequence, the /HIT output is driven low At the end of any write
sequence (after /CAL and /WE are brought high and t
RE
is satisfied),
/RE can be brought high to precharge the memory Cache reads can
be performed concurrently wth precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads wll occur from
the page accessed during the last /RE active read cycle. During write
sequences, a write operation is not performed unless both /CAL and
/WE are low As a result, the /CAL input can be used as a byte write
select in multi-chip systems.
DRAMWrite Mss
A DRAMwrite request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAMwll compare the newrow
address to the LRR address latch for the bank specified for row
address bits A
8-9
(LRR: a 9-bit rowaddress latch for each internal
DRAMbank which is reloaded on each /RE active read mss cycle).
If the rowaddress does not match any of the LRRs, the EDRAMwll
write data to the DRAMpage in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAMas soon as the column address is
latched by bringing /CAL lowand the write data is latched by
bringing /WE low(both /CAL and /WE must be high when initiating
the write cycle wth the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for
the column address and t
DS
for the data). During a write burst
sequence, the second write data can be posted at time t
RSW
after
/RE. Subsequent writes wthin a page can occur wth write cycle
time t
PC
. During a write mss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory Cache
reads can be performed concurrently wth the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads wll
occur fromthe page accessed during the last /RE active read cycle.
During write sequences, a write operation is not performed unless
both /CAL and /WE are low As a result, /CAL can be used as a byte
write select in multi-chip systems.
/RE Inactive Operation
Data may be read fromthe SRAMcache wthout clocking /RE.
This capability allows the EDRAMto performcache read
operations during precharge and refresh cycles to mnimze wait
states. It is only necessary to select /S and /Gand provide the
appropriate column address to read data as shown in the table
below In this mode of operation, the cache reads wll occur from
the page accessed during the last /RE active read cycle. To perform
a cache read in static column mode, /CAL is held high, and the
cache contents at the specified column address wll be valid at time
t
AC
after address is stable. To performa cache read in page mode,
/CAL is clocked to latch the column address. When /RE is inactive,
the hit pin is not driven and is in a high impedance state.
This option is desirable when the external control logic is
capable of fast hit/mss comparison. In this case, the controller can
avoid the time required to performrow/column multiplexing on hit
cycles.
EDOMode andOutput LatchEnabe Operation
The QLE and /CAL inputs can be used to create extended data
output (EDO) mode timngs in either static column or page modes.
The 512K x 8 EDRAMhas an output latch enable (QLE) that can be
used to extend the data output valid time. The output latch enable
operates as shown in the followng table.
When QLE is low the latch is transparent and the EDRAM
operates identically to the standard 4Mx 1 and 1Mx 4 EDRAMs.
When /CAL is high during a static column mode read, the QLE input
can be used to latch the output to extend the data output valid time.
QLE can be held high during page mode reads. In this case, the
data outputs are latched while /CAL is high and open when /CAL is
not high.
When output data is latched and /S goes high, data does not go
Hi-Z until /Gis disabled or either QLE or /CAL goes lowto unlatch
data.
Write-Per-Bit Operation
The DM2213 version of the 512Kb x 8 EDRAMoffers a write-
per-bit capability which allows single bits of the memory to be
selectively written wthout altering other bits in the same word. This
capability may be useful for implementing parity or masking data in
video graphics applications. The bits to be written are determned
by a bit mask data word which is placed on the I/Odata pins DQ
0-7
prior to clocking /RE. The logic one bits in the mask data select the
bits to be written. As soon as the mask is latched by /RE, the mask
data is removed and write data can be placed on the databus. The
mask is only specified on the /RE transition. During page mode
burst write operations, the same mask is used for all write
operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the rowaddress supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/CAL Before /RE Refresh(“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section.
Function
/S
/CAL
A
0-7
/G
Cache Read (Static Column)
L
L
H
Col Adr
Cache Read (Page Mode)
L
L
¤
Col Adr
QLE
L
/CAL
Comments
Output Transparent
X
Output Latched When QLE=H (Static Column EDO)
H
H
Output Latched When /CAL=H (Page Mode EDO)
¤
¤
相關(guān)PDF資料
PDF描述
DM1M36SJ-10 Enhanced DRAM (EDRAM) Module
DM1M36SJ6-10 Enhanced DRAM (EDRAM) Module
DM2200J-10 Enhanced DRAM (EDRAM)
DM2202J-10 Enhanced DRAM (EDRAM)
DM2203T-12 Enhanced DRAM (EDRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM1R24A5 制造商:M.E.C. TIMERS 功能描述: 制造商:M.E.C. Timers 功能描述:
DM1S-H3-A-07R5-02N 制造商:HEINEMANN / EATON 功能描述:
DM1S-S3-A-10-2 制造商:HEINEMANN / EATON 功能描述:
DM1S-S3-A-20-2 制造商:HEINEMANN / EATON 功能描述:
DM1S-S3-A-30-2 制造商:HEINEMANN / EATON 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*