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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DLP-FPGA-M |
| 寤犲晢锛� | DLP Design Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 7/10闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MODULE USB-TO-FPGA TOOL W/MANUAL |
| 妯欐簴鍖呰锛� | 1 |
| 涓昏鐩殑锛� | 鎺ュ彛锛孶SB 鑷� FPGA |
| 宓屽叆寮忥細 | 鏄�锛孎(xi脿n)PGA / CPLD |
| 宸茬敤 IC / 闆朵欢锛� | FT2232D锛孹C3S250E-4TQ144 |
| 涓昏灞€э細 | USB 鑷� FPGA锛�40 I/O 寮曡叧锛孲RAM: 128k x 8 |
| 娆¤灞€э細 | 鎵嬪唺涓湁 4 鍊嬪椹楀锛�250k 绯荤当(t菕ng)鏌垫サ锛�5.5k 閭忚集鍠厓 |
| 宸蹭緵鐗╁搧锛� | 鏉匡紝鎵嬪唺 |
| 鐩搁棞(gu膩n)鐢�(ch菐n)鍝侊細 | XC3S250E-4TQG144I-ND - IC FPGA SPARTAN-3E 250K 144-TQFP 768-1010-6-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-1-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-2-ND - IC USB FS DUAL UART/FIFO 48-LQFP 122-1524-ND - IC SPARTAN-3E FPGA 250K 144TQFP |
| 鍏跺畠鍚嶇ū锛� | 813-1009 |
Rev. 1.4 (November 2010)
6
DLP Design, Inc.
T
TA
AB
BL
LE
E 1
1
NN (dec)*
NN (hex)*
Name
FPGA Pin
JP2 Pin
0
user_io(0)
U5 Pin 58
JP2 Pin 2
1
user_io(1)
U5 Pin 59
JP2 Pin 4
2
user_io(2)
U5 Pin 93
JP2 Pin 5
3
user_io(3)
U5 Pin 94
JP2 Pin 6
4
user_io(4)
U5 Pin 96
JP2 Pin 7
5
user_io(5)
U5 Pin 97
JP2 Pin 8
6
user_io(6)
U5 Pin 103
JP2 Pin 9
7
user_io(7)
U5 Pin 104
JP2 Pin 10
8
user_io(8)
U5 Pin 105
JP2 Pin 12
9
user_io(9)
U5 Pin 106
JP2 Pin 13
10
A
user_io(10)
U5 Pin 112
JP2 Pin 14
11
B
user_io(11)
U5 Pin 113
JP2 Pin 15
12
C
user_io(12)
U5 Pin 116
JP2 Pin 16
13
D
user_io(13)
U5 Pin 117
JP2 Pin 17
14
E
user_in(14) [INPUT ONLY!]
U5 Pin 119
JP2 Pin 18
15
F
user_in(15) [INPUT ONLY!]
U5 Pin 120
JP2 Pin 19
16
10
user_io(16)
U5 Pin 122
JP2 Pin 20
17
11
user_io(17)
U5 Pin 123
JP2 Pin 21
18
12
user_io(18)
U5 Pin 124
JP2 Pin 22
19
13
user_io(19)
U5 Pin 125
JP2 Pin 27
20
14
user_io(20)
U5 Pin 126
JP2 Pin 29
21
15
user_io(21)
U5 Pin 130
JP2 Pin 30
22
16
user_io(22)
U5 Pin 131
JP2 Pin 31
23
17
user_io(23)
U5 Pin 132
JP2 Pin 32
24
18
user_io(24)
U5 Pin 134
JP2 Pin 33
25
19
user_io(25)
U5 Pin 135
JP2 Pin 34
26
1A
user_io(26)
U5 Pin 139
JP2 Pin 35
27
1B
user_io(27)
U5 Pin 140
JP2 Pin 36
28
1C
user_io(28)
U5 Pin 142
JP2 Pin 37
30
1E
user_in(0)
U5 Pin 10
JP2 Pin 49
31
1F
user_in(1)
U5 Pin 12
JP2 Pin 48
32
20
user_in(2)
U5 Pin 29
JP2 Pin 47
33
21
user_in(3)
U5 Pin 31
JP2 Pin 46
34
22
user_in(4)
U5 Pin 36
JP2 Pin 45
35
23
user_in(5)
U5 Pin 38
JP2 Pin 44
36
24
user_in(6)
U5 Pin 41
JP2 Pin 43
37
25
user_in(7)
U5 Pin 47
JP2 Pin 42
38
26
user_in(8)
U5 Pin 48
JP2 Pin 41
39
27
user_in(9)
U5 Pin 66
JP2 Pin 39
40
28
user_in(10)
U5 Pin 69
JP2 Pin 38
Read: 29,
>40
Read:1D,
>29
Returns Read Pin Error E4
n/a
Write: 14,
15, >30
Write: E, F,
>1E
Returns Write Pin Error E2 for Pin
Clear (low), or E3 for Pin Set
(high)
n/a
Ground
1,11,25,26,40,50
FPGA_RESET
128
3
5VIN 鈥� Module power source
23
PORTVCC 鈥� Power from Host PC
24
VCCSW 鈥� 5V power after host
enumerates the USB port
28
**N
No
otte
e:: This is the I/O number for use with the Test Bit File described in Section 7.
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