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參數(shù)資料
| 型號(hào)： | DLP-FPGA-M |
| 廠商： | DLP Design Inc |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MODULE USB-TO-FPGA TOOL W/MANUAL |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，USB 至 FPGA |
| 嵌入式： | 是，F(xiàn)PGA / CPLD |
| 已用 IC / 零件： | FT2232D，XC3S250E-4TQ144 |
| 主要屬性： | USB 至 FPGA，40 I/O 引腳，SRAM: 128k x 8 |
| 次要屬性： | 手冊(cè)中有 4 個(gè)實(shí)驗(yàn)室，250k 系統(tǒng)柵極，5.5k 邏輯單元 |
| 已供物品： | 板，手冊(cè) |
| 相關(guān)產(chǎn)品： | XC3S250E-4TQG144I-ND - IC FPGA SPARTAN-3E 250K 144-TQFP 768-1010-6-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-1-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-2-ND - IC USB FS DUAL UART/FIFO 48-LQFP 122-1524-ND - IC SPARTAN-3E FPGA 250K 144TQFP |
| 其它名稱(chēng)： | 813-1009 |
Rev. 1.4 (November 2010)
3
DLP Design, Inc.
Chapter 4: Lab 3: Memory Test: Block Diagram, DCM Design, SRAM State Machine, Bi-Directional
Buffers, Test Failed Indicator, User Constraint File, Synthesize the Memory Test Design, Simulate the
Memory Test Design, Implementing the Design, Download the Design to the FPGA
Chapter 5: Lab 4: USB Loopback: Initial Design, USB State Machine Module, Language Template,
Bi-Directional Buffers, Synthesize, Simulate, Pin Constraints, Implement, Download the Design to the
FPGA
(The completed design files for each lab are available for download from the DLP Design website
upon purchase of the DLP-FPGA and Lab Manual.)
3.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-FPGA is the Xilinx Spartan 3E:
XC3S250E-4TQ144.
Part Number: XC3S250E
System Gates: 250K
Equivalent Logic Cells: 5,508
CLB Array
o
Rows: 34
o
Columns: 26
o
Total CLB’s: 612
o
Total Slices: 2,448
Distributed RAM Bits: 38K
Block RAM Bits: 216K
Dedicated Multipliers: 12
DCM’s: 4
4.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-FPGA that will load an FPGA configuration (.bit)
file directly to the SPI Flash device via the USB interface. This app (shown below) will allow the user
to erase the flash, verify the erasure and then program and verify the flash:
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