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參數(shù)資料
| 型號： | DJCE6353882077 |
| 廠商： | INTEL CORP |
| 元件分類： | 接收器 |
| 英文描述： | Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) |
| 中文描述： | VIDEO DISCRIMINATOR, QFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 322K |
| 代理商： | DJCE6353882077 |
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CE6353
Data Sheet
19
Intel Corporation
3.2.2 MPEG Data Output Signals
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in
the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running
clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with
MOCLKINV = ‘1’, the default state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
Figure 7 - MPEG Output Data Waveforms
3.2.3 MPEG Output Timing
Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80
o
C, Output load = 10pF.
Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10
o
C, Output load = 10pF.
MOCLK frequency = 45.06 MHz.
MDO7:0
MOCLKINV=1
MOCLK
MOSTRT
MOVAL
BKERR
Tp
Ti
1st byte packet n
188 byte packet n
1st byte packet n+1
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相關(guān)代理商/技術(shù)參數(shù) |
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| DJCE6353SL9EN882128 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) |
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