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| 型號(hào)： | DISADVANTAGE |
| 英文描述： | Disadvantage of On-Chip Transient Protection (105k) |
| 中文描述： | 缺點(diǎn)片上瞬態(tài)保護(hù)（大多數(shù)人105K） |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | DISADVANTAGE |
2
www.semtech.com
PROTECTION PRODUCTS
structure, the on-chip diodes shunt the transient
current to the power line (VCC) or ground. A positive
transient voltage causes diode D1 to be forward
biased when the input voltage exceeds VCC. Likewise,
for negative transients, Diode D2 shunts the negative
current. The polysilicon input resistors serve to limit
the peak currents. Since polysilicon resistors are
thermally insulated by a surrounding layer of SiO
2
or
glass they are particularly susceptible to thermal
damage resulting from joule heating by ESD induced
currents. A typical CMOS input protection circuit can
provide ESD immunity to approximately 4kV.
Alternative Protection Schemes
SI97-04
Surging
Ideas
TVS Diode Application Note
On-chip protection should be viewed as a secondary
measure only and should not be relied upon as the
sole protection method. The first reason is that
placement of the protection element is critical. ESD
induced transients can be coupled into nearby traces
including data lines, clock signal lines, and power
supply rails (Figure 2a). Additionally, the magnitude of
the voltage across the chip is increased due to Ldi/dt
effect and can exceed the capability of the input
protection network (Vpk = VESD + Ldi/dt).
External protection elements designed to absorb high
levels of transient energy are normally required to
provide reliable ESD/EOS protection, even if the
protected device includes some form of on-chip protec-
tion
. For protection of data and I/O ports, the external
protection element should be placed near the signal
entry point. By diverting the transient to ground
immediately, radiation to nearby circuitry is reduced
(Figure 2b). While many devices may offer protection
for ESD induced transients, they offer little or no
protection for longer duration pulses such as those
associated with lightning. This is especially critical for
equipment with outside line connections such as point-
of-sale systems and cellular base stations.
Design Example
Figure 3 illustrates how to protect a typical 3 x 5 RS-
232 Driver/Receiver (NSC DS14185) using Semtech’s
SMDA24C-8 TVS array. The SMDA24C-8 is designed to
protect 8 bidirectional I/O lines operating at 12V. The
DS14185 transceiver has internal ESD protection to
2.5kV. The addition of the SMDA24C-8 increases the
ESD protection to >15kV. This combination offers a
low cost, high reliability solution to aid in meeting the
requirements of IEC 61000-4-2. As always, ESD/EOS
protection is recommended at the power supply rails
as well as the I/O interface. Semtech SM05 and
SM12 are used to protect the 5V and 12V supplies
respectively. Finally, while TVS diodes are necessary
for suppression of conducted transients, good pc
board layout and equipment shielding is required to
guard against electromagnetic coupling and externally
radiated events.
References:
1
Greason, William D., “
Electrostatic Damage in
Electronics: Devices and Systems
”, Research
Studies Press Ltd., 1989.
Russell, William, “
Protecting Portable Devices from
ESD Damage
”, Communications Systems Design
Magazine, April, 1997
National Semiconductor Corporation, Interface
Products Databook, 1996
2
3
Figure 3 - RS-232 Design Example
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