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| 型號： | DISADVANTAGE |
| 英文描述： | Disadvantage of On-Chip Transient Protection (105k) |
| 中文描述： | 缺點片上瞬態(tài)保護（大多數(shù)人105K） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 105K |
| 代理商： | DISADVANTAGE |
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www.semtech.com
PROTECTION PRODUCTS
Disadvantage of On-chip Transient Protection
SI97-04
Surging
Ideas
TVS Diode Application Note
Revision 9/2000
Relying upon on-chip protection to suppress ESD/EOS
events may provide a false sense of security if not
carefully evaluated. In the past, 2kV-4kV of on-chip
ESD protection was thought to be adequate protec-
tion. New standards such as IEC 61000-4-2 have
raised the minimum protection level to as much as
15kV. As device geometries continue to shrink, it is
becoming more difficult to add on-chip protection with
a common manufacturing process. As a result, de-
vices operating at low voltages may not be adequately
protected. This application note will discuss the disad-
vantages of on-chip protection and provide the de-
signer with applications information for adding external
protection components to insure maximum ESD/EOS
immunity.
Typical CMOS input protection
Some integrated circuits feature built in protection by
means of an internal SCR or resistor and diode net-
work. The basic requirements of a protection network
are that it provide a low impedance path for the
discharge energy while limiting the current and voltage
seen by the active circuit. This means that the tran-
sient energy is dissipated in the transceiver itself. The
Figure 1 - Typical CMOS Input Protection Scheme
Figure 2a - IC with Internal ESD Protection
Figure 2b - TVS Diode Protection Points
basic input protection circuit usually consists of the
following elements:
z
A shunt device to discharge positive polarity tran-
sients
A shunt device to discharge negative polarity
transients
A series element for current limiting
z
z
A typical CMOS input protection circuit is shown in
Figure 1. When an ESD voltage is applied to the input
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