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參數(shù)資料
| 型號(hào)： | DIR1703E |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 236K |
| 代理商： | DIR1703E |
SLES007
–
JULY 2001
16
www.ti.com
reset sequence
The DIR1703 requires external reset operation after power on. Figure 10 shows the reset sequence after power
on. The DIR1703 is ready for receiving S/PDIF signal when the internal reset sequence has finished and
CKTRNS goes to LOW. BFRAME, EMFLG, URBIT and CSBIT pins are used for configuration during the period
from the rising edge of RST to the falling edge of CKTRNS. S/PDIF signal is accepted after CKTRNS goes to
LOW. The minimum pulse width of RST, t
RST
is 100 ns. The RST delay after the power supply reaches 3 V should
be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW.
LOW
HIGH
LOW
HIGH
HIGH
Chip Status Information
LOW
Unstable
Stable
3 V
VDD, VCC
XTI
XTO
RST
BFRAME,
EMFLG,
VRBIT,
CSBIT
CKTRNS
DIN
UNLOCK
DIR1703 Ready
Internal PLL ON
tSTT > 10 ms
tRST > 100 ns
12.5XTI Clock
Unknown
Valid
1160XTI Clock
< 5 fs
S/PDIF Acceptable
< 1 ms
NOTE: SCF0 and SCF1 should be settled during RST assertion. The change of SCF0 and SCF1 is not permitted during normal operation. When
the change is needed, the reset sequence must be started by asserting RST again.
Figure 10. After Power ON
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DISADVANTAGE | Disadvantage of On-Chip Transient Protection (105k) |
| DISCONTINUEDPRODUCTS | Discontinued Products - August 2. 1999 |
| DISPLAY-XREF | Optoelectronic |
| DIV100 | DIV100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| DJ25E | Proximity Sensors Inductive ABS Housing |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
| DIR-605L/E | 制造商:D-Link Networks 功能描述: |
| DIR-615/E | 制造商:D-Link Networks 功能描述: |
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