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參數(shù)資料
| 型號(hào)： | DIR1703 |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 236K |
| 代理商： | DIR1703 |
SLES007
–
JULY 2001
6
www.ti.com
basic operation theory
The DIR1703 is operated as either a PLL clock operation mode or a crystal clock operation mode. These basic
operation modes are user selectable.
Sampling period adaptive controlled tracking system (SpAct) is a newly developed clock recover architecture,
giving very low jitter clock from S/PDIF data input.
The DIR1703 has two PLLs, PLL1 and PLL2. SpAct is supplied with a 100 MHz executing clock from PLL1.
The DIR1703 requires system clock input for operation of SpAct at both the PLL clock operation mode and the
crystal clock operation mode. This system clock can be obtained by connecting a crystal resonator at the
XTI/XTO pins or applying an external clock input at the XTI pin as shown in Figure 1.
PLL2 generates the system clock SCKO by using the output signal of the SpAct. The source of SCKO, either
OSC (crystal) or PLL2, is selected by the CKSEL pin (called PLL clock operation mode and crystal clock
operation mode).
In the PLL clock operation mode, when the S/PDIF signal goes to noninput, SCKO may hold the latest tracked
frequency.
Also, the DIR1703 indicates the unlocked state by a high level output at the UNLOCK pin. When the S/PDIF
signal restarts, the analog PLL will lock to the incoming S/PDIF signal with very low jitter. The PLL lock-in time
is around 1 ms using the SpAct.
Then, the DIR1703 indicates the locked status by a low output at the UNLOCK pin. In this status, the BRATE
pins simultaneously indicate the bit rate of the incoming S/PDIF signal.
After RST
(pin 21) is removed, SCKO is set to the default frequency, which can be selected by the BRSEL and
SCF pins. The sampling rate (f
S
), 32 k, 44.1 k, 48 k, 88.2 k, or 96 k is selected by the BRSEL pin. The system
clock frequency, 128, 256, 384, or 512 f
S
is also selected by the SCF pins.
In the crystal clock operation mode, the crystal oscillator generates three audio clocks SCKO, BCKO, and
LRCKO. In this mode, DOUT is always set to mute (zero). BRATE and UNLOCK can be indicated according
to the incoming S/PDIF signal.
If CKSEL (pin 28) is connected to UNLOCK (pin 27), which indicates the S/PDIF decoding status and the PLL2
lock-state, the system clock source can be selected automatically when the S/PDIF signal is active and the bit
rate is detected.
Crystal
C1
DIR1703
XTO
XTI
Open
DIR1703
XTO
XTI
C2
R1 = 1 M
,
C1, C2 = 10 TO 33 pF
Crystal Resonator Connection
XTAL
OSC
CIR
XTAL
OSC
CIR
External Clock
R1
External Clock Input
Figure 1. System Clock Connections
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DIR1703E | DIGITAL AUDIO INTERFACE RECEIVER |
| DISADVANTAGE | Disadvantage of On-Chip Transient Protection (105k) |
| DISCONTINUEDPRODUCTS | Discontinued Products - August 2. 1999 |
| DISPLAY-XREF | Optoelectronic |
| DIV100 | DIV100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DIR1703E | 功能描述:IC DIGTAL AUD INTRFC RCVR 28SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,240 系列:GD 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):3/5 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:20-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:20-PDIP 包裝:管件 |
| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
| DIR-605L/E | 制造商:D-Link Networks 功能描述: |
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