參數(shù)資料
型號(hào)： DIR1701E2K
英文描述： DIGITAL AUDIO INTERFACE RECEIVER
中文描述： 數(shù)字音頻接口接收機(jī)
文件頁(yè)數(shù)： 8/19頁(yè)
文件大小： 290K
代理商： DIR1701E2K
DIR1701
SLAS331
–
APRIL 2001
8
www.ti.com
SCKO timing
L
H
0.8 V
2 V
System Clock Pulse
Cycle Time
tSCKH
tSCKL
SCKO
SCKO Clock Pulse Width High
SCKO Clock Pulse Width Low
1/128 fS, 1/256 fS, 1/384 fS or 1/512 fS.
tSCKH
tSCKL
7 ns (min)
7 ns (min)
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1701 detects automatically
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 5 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 5. Incoming Sample Frequency Bits
SAMPLING RATE
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
BRATE1
HIGH
LOW
LOW
HIGH
HIGH
BRATE0
HIGH
LOW
HIGH
LOW
LOW
timing specification for PLL operation
lock-up time
Lock
L
H
tINT< 1 ms
Unlock
DIN Start
PLL
Condition
PLL Status
Indicator Pin
Site UNLOCK
Figure 3. PLL Lock Up Timing
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DISADVANTAGE Disadvantage of On-Chip Transient Protection (105k)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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