- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378545 > DF1760 Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM PDF資料下載
參數(shù)資料
| 型號(hào)： | DF1760 |
| 英文描述： | Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM |
| 中文描述： | 多位增強(qiáng)噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng) |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 201K |
| 代理商： | DF1760 |
PCM1760P/U DF1760P/U
8
FUNCTIONS OF
THE DIGITAL FILTER
SYSTEM CLOCK
The DF1760 can accept a system clock of either 256fs or
384fs. If a 384fs system clock is used, the DF1760 divides
by 2/3 to create the 256fs system clock required for the
PCM1760. The system clock is applied to pin 15 (SYSCLK
input). The actual clock selection is done by setting pin 25
(CLKSEL input) “high” for 256fs clock and “LOW” for
384fs clock.
The detailed timing requirements for the system clock are
shown in Figure 3c.
CLKSEL
SYSCLK
H
L
256fs
384fs
MASTER/SLAVE MODE
The DF1760 can be used in both the master mode and slave
mode. In the master mode, the DF1760 outputs L/R (left/
right channel phase clock), SCLK (data clock) and FSYNC
(frame clock 2fs) signals. In the slave mode, the DF1760
accepts L/R, SCLK and FSYNC signals. The mode selection
is done by taking pin 24 (S/M INPUT) “HIGH” for slave
mode and “LOW” for master mode.
S/M
MODE
H
L
Slave
Master
OUTPUT DATA FORMAT
The serial output data has four possible formats. The selec-
tion of the formats can be done by the Mode 1 and Mode 2
inputs.
CALD
CALIBRATION
H
L
Disable
Enable
MODE 1
MODE 2
FORMATS
H
L
H
L
H
H
L
L
MSB First, 16 Bits, Falling Edge
MSB First, 20 Bits, Falling Edge
MSB First, 20 Bits, Rising Edge
LSB First, 20 Bits, Falling Edge
LRSC
L/R CLOCK AND CHANNEL
H
H = LCH,
L = RCH
L
L = LCH,
H = RCH
OVERFLOW DETECTION
When a near-to-clipping input condition is detected, OVL
output (Pin 1), or OVR output (Pin 2), becomes “HIGH” for
a duration of 4096/fs (about 85ms) depending upon on the
channel detected.
The OVL and OVR output return to “LOW” after
4096/fs duration automatically.
OFFSET CALIBRATION MODE
The offset error is calibrated by storing the digital data when
the input is zero in registers and subtracting it from the
future data with actual signal input.
To enable the calibration mode, set the CALD input (Pin 13)
“LOW”. The calibration mode is disabled by setting the
CALD input (Pin 13) “HIGH”. The calibration cycle is
initiated by setting the /PD input (Pin 21) “LOW” for more
than 2 system clock periods and then setting it “HIGH”.
During the calibration cycle, the CAL output (Pin 14)
becomes “HIGH”, all the serial data is forced to “LOW”,
and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19)
pins become input terminals after the completion of the
calibration cycle. The CAL output is “LOW”.
POWER DOWN MODE/RESET
The /PD input (Pin 21) has two functions. First, it should be
set at “HIGH” after application or restoration of power (V
SS
and/or V
) to accomplish the power-on/mode reset func-
tion. The detail timing requirements for this function are
shown in Figure 3f. Second, the DF1760 is placed in the
power down mode by setting the /PD input (Pin 21) “LOW”.
Set the /PD input (Pin 21) “HIGH” for normal operation
mode.
LR CHANNEL PHASE CLOCK
The status of the LR channel phase clock can be set by the
LRSC input.
/PD
OPERATION
H
L
Normal
Power Down
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
Delay from Overflow Detection
to OVL (OVR) Output
T
OR
T
OF
–
–
0
ns
OVL (OVR) Output Pulse Width
–
4096
–
1/fs
FIGURE 3a. DF1760 Overflow Detection.
T
OF
T
OR
T
OF
T
OR
OVL (OVR)
–Detect Level
+Detect Level
The power dissipation of the DF1760 in the power down
mode is about 1/10 of the normal operation mode. During
the power down mode, the L/R, SCLK, and FSYNC pins
become input pins and all the serial data is forced “LOW”.
The 256fs output is enabled even in the power down mode.
The detailed timing of the power down mode operation and
the offset calibration is shown in Figure 3b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DF1B-R28A | MOSFET N-CH 500V 64A SOT-227 |
| DF1B-28PRB | 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard) |
| DF1B-28PRF | 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard) |
| DF1B-28PRFB | 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard) |
| DF1B-R28F | 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DF17-60DP-0.5V | 制造商:HRS 制造商全稱:HRS 功能描述:0.5mm Pitch Board to Board Connector |
| DF17-60DS-0.5V | 制造商:HRS 制造商全稱:HRS 功能描述:0.5mm Pitch Board to Board Connector |
| DF1760P | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Ind Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DF1760U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Ind Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DF1760U/1K | 功能描述:IC PCM1760 DIGITAL FILTER 20-SOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。