參數(shù)資料
型號(hào)： DF1760
英文描述： Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
中文描述： 多位增強(qiáng)噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng)
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 201K
代理商： DF1760
PCM1760P/U DF1760P/U
12
ANALOG INPUT
CONDITION
DIGITAL OUTPUT
+2.55V
+2.50V to +2.55V
+2.50V
0V
–2.50V
–2.83V to –2.85V
–2.85V
+Max Input
Overflow
+FSR
BPZ (Ideal)
–FSR
Overflow
–Max Input
72000H
70000H to 72000H
(2)
70000H
00000H
(1)
90000H
82FFFH to 82000H
(2)
82000H
NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over
70000H or under 82FFFH of digital output code.
TABLE I. Output Codes.
POWER SUPPLY SEQUENCING
The PCM1760 requires
±
V
CC
and
±
V
DD
power supplies. To
avoid any possibility of latch-up, the
±
V
CC
and
±
V
DD
power
should all be applied simultaneously or the +V
CC
and +V
DD
applied first followed by –V
CC
and –V
DD
.
FIGURE 10. Illustration of Offset Calibration.
+fs
BPZ
–fs
0V
+fs
–fs
ANALOG INPUT
V
OS
D
+fs
BPZ
–fs
0V
+fs
–fs
ANALOG INPUT
D
Analog Input
V
OS
PCM1760
DF1760
CAL
PD
V
OS
POWER-ON RESET AND MODE RESET
The timing requirements for POWER-ON RESET and
MODE RESET are shown in Figure 3f. The DF1760 re-
quires POWER-ON RESET when power is applied or re-
stored. MODE RESET is required when any of the follow-
ing has been changed: system clock, master/slave mode,
output data format, L/R clock, calibration after POWER-ON
in slave mode.
This reset should be done by holding the /PD input (pin 21)
low for more than 2/fs. Suggested reset circuits are given in
Figures 11, 12 and 13.
CLOCK INPUT
After power is applied to the DF1760, the system clock
should be provided continuously. The DF1760 employs a
dynamic logic architecture.
相關(guān)PDF資料
PDF描述
DF1B-R28A MOSFET N-CH 500V 64A SOT-227
DF1B-28PRB 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard)
DF1B-28PRF 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard)
DF1B-28PRFB 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard)
DF1B-R28F 2.5mm Pitch Connector for Discrete Wire Connection (Product Compliant with UL/CSA Standard)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DF17-60DP-0.5V 制造商:HRS 制造商全稱(chēng):HRS 功能描述:0.5mm Pitch Board to Board Connector
DF17-60DS-0.5V 制造商:HRS 制造商全稱(chēng):HRS 功能描述:0.5mm Pitch Board to Board Connector
DF1760P 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Ind Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DF1760U 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Ind Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DF1760U/1K 功能描述:IC PCM1760 DIGITAL FILTER 20-SOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:-
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*