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參數(shù)資料
| 型號： | DEM-VSP2232Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 248K |
| 代理商： | DEM-VSP2232Y |
VSP2232
SLAS320
–
MAY 2001
16
www.ti.com
timing specifications (continued)
t(XS)
t(CKH)
t(CKL)
t(CKP)
t(XH)
MSB
LSB
2-Bytes
SLOAD
SCLK
SDATA
t(DS)
t(DH)
PARAMETER
MIN
TYP
MAX
UNIT
t(CKP)
t(CKH)
t(CKL)
tsu
th
t(XS)
t(XH)
NOTES: 10. It is effective for the data shift operation at the rising edges of SCLK during SLOAD is low period. 2 bytes of data input are loaded
to the parallel latch in the VSP2232 at the rising edge of SLOAD.
11. When the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the former bits are lost.
Clock period
100
ns
Clock high pulse width
40
ns
Clock low pulse width
40
ns
Data setup time
30
ns
Data hold time
30
ns
SLOAD to SCLK setup time
30
ns
SCLK to SLOAD hold time
30
ns
Figure 5. VSP2232 Serial Interface Timing Specification
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