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參數(shù)資料
| 型號： | DEM-PCM3000 |
| 英文描述： | DEM-PCM3000 - EVALUATION FIXTURE |
| 中文描述： | DEM的PCM3000 -評價夾具 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 221K |
| 代理商： | DEM-PCM3000 |
DEM-PCM1702P
3
OPERATION MODE SELECT SWITCH
The Operation Mode Select switch provides for the selection
of dither, system clock and input format as described in the
tables below.
NAME
FUNCTION
L
H
DITHN
Dither Select
Dither On
Dither Off
CLKSL
System Clock Select
256fs
384fs
1W1N (2N)
Input Format Select
Table of Below
INPUT FORMAT
1W1N
1W2N
MSB First, Right-justified, 16-Bit
MSB First, Right-justified, 18-Bit
MSB First, Right-justified, 20-Bit
MSB First, Right-justified, 24-Bit
H
L
H
L
H
H
L
L
For detailed timing infomation, see the data sheet for the NPC SM5842AP.
From the factory, these switches are set to provide for no
dither, system clock equal 256fs and data format set for MSB
first, right justified, 20-bit, as shown below.
D
I
T
H
N
C
L
K
S
L
N
1
W
1
N
H
(Standard P
L
H
L
L
H
1
W
2
N
FIGURE 3. Opearation Mode Select Switch.
OPTIONAL FUNCTION JUMPERS
The optional functions of right and left channel de-empha-
sis, the de-emphasis system clock, and right and left channel
mute are controlled by jumpers J1 through J6 as shown in
the following table.
JUMPER #
FUNCTION
JUMPER
NO JUMPER
J1
De-emphasis, Rch
OFF
ON
J2
De-emphasis, Lch
OFF
ON
J3
De-emphasis, fs-32kHz
X
J4
De-emphasis, fs-32kHz
X
J3
De-emphasis, fs-41.4kHz
X
J4
De-emphasis, fs-41.4kHz
X
J3
De-emphasis, fs-48kHz
X
J4
De-emphasis, fs-48kHz
X
J5
Mute, Rch
No Mute
Mute
J6
Mute, Lch
No Mute
Mute
From the factory, Jumpers J1, J2, J5 and J6 are installed, as
shown below, setting the system clock at 32kHz, no de-
emphasis and no mute.
FIGURE 4. Optional Function Jumpers.
SYSTEM CLOCK OPERATION
A system clock (SYSCLK) is required for operation of the
DEM-PCM1702. If the DEM-PCM1702 is being used with
the DEM-PCM1760, the 256fs or 384fs system clock is
provided by the DEM-PCM1760 through pin 16 of the
Interface Connector, as described below. (NOTE: Care must
be taken to insure both boards are set to the same master
clock.)
If the DEM-PCM1702 is being used where it must generate
the 256fs or 384fs master clock, the appropriate crystal can
be connected to the SM5842.
COMBINATION WITH DEM-PCM1760
The DEM-PCM1702 can be directly combined with the
DEM-PCM1760 (20-bit stereo A/D conversion system).
In this case, the connector pins of the DEM-PCM1702 and
the DEM-PCM1760 are connected directly together.
The power supply for the DEM-PCM1760 is provided by
the DEM-PCM1702 and the serial digital data (within sys-
tem clock) is provided to the DEM-PCM1702 from the
DEM-PCM1760.
J1
J2
J3
J4
J5
J6
FIGURE 5. Combination with DEM-PCM1760.
Power
Supply
for
Digital:
+5V
Power
Supply
for
Analog:
±9V
to ±12V
Analog In
Analog Out
Jumper Line
DEM-PCM1702
DEM-PCM1760
CN1 CN2
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