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參數(shù)資料
| 型號(hào)： | DDU18-72C4 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 延遲線 |
| 英文描述： | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, DSO24 |
| 封裝： | SMD-24 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 233K |
| 代理商： | DDU18-72C4 |
DDU18
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
oC ± 3oC
Load:
50
to -2V
Supply Voltage (Vcc): -5.0V
± 0.1V
Cload:
5pf
± 10%
Input Pulse:
Standard 10KH ECL
Threshold:
(VOH + VOL) / 2
levels
(Rising & Falling)
Source Impedance:
50
Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 10 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
T2
T3
T4
T5
T6
T7
T8
Timing Diagram For Testing
DRISE
DFALL
PERIN
PWIN
TRISE
TFALL
20%
50%
80%
50%
V
VIL
VOH
VOL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #97041
DATA DELAY DEVICES, INC.
4
5/5/04
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDU18-72MC4 | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-80C4 | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-80MC4 | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-8C4 | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-8MC4 | 8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU18-72M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-72MC3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU18-72MC4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:8-TAP, ECL-INTERFACED FIXED DELAY LINE FIXED DELAY LINE |
| DDU18-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| DDU18-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
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