參數(shù)資料
型號(hào)： DDC114YK-7
廠商： DIODES INC
元件分類： 功率晶體管
英文描述： NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
中文描述： 70 mA, 50 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR
封裝： PLASTIC PACKAGE-6
文件頁數(shù)： 5/30頁
文件大小： 389K
代理商： DDC114YK-7
""#
SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
5
PIN CONFIGURATIONS
Top View
QFN
36
35
34
33
32
31
30
29
28
27
26
25
DIN
DIN
NC
NC
RESET
TEST
DGND
DGND
AGND
AVDD
AGND
AGND
D
D
C
D
D
D
C
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
DOUT
DOUT
CLK_4X
FORMAT
HISPD/LOPWR
RANGE0
RANGE1
RANGE2
AGND
VREF
AGND
AGND
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DDC114
PIN DESCRIPTIONS
PIN
DOUT
DOUT
CLK_4X
FORMAT
HISPD/LOPWR
RANGE0
RANGE1
RANGE2
NUMBER
1
2
3
4
5
6
7
8
9, 11-14, 16, 18-20,
22, 24-26, 28
10
15
17
21
23
27
29, 30, 38, 41, 43, 45,
47, 48
31
32
33, 34
35
36
37
39
40
42
44
46
FUNCTION
Digital Output
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
DESCRIPTION
Serial Data Output
Serial Data Output: Complementary Signal
Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4
Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits
Mode Control: 0 = Low Power, 1 = High Speed
Range Control 0 (least significant bit)
Range Control 1
Range Control 2 (most significant bit)
AGND
Analog
Analog Ground
VREF
AIN4
AIN3
AIN2
AIN1
AVDD
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog
External Voltage Reference Input, 4.096V Nominal
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Power Supply, 5V Nominal
DGND
Digital
Digital Ground
TEST
RESET
NC
DIN
DIN
DVDD
DCLK
DCLK
CLK
DVALID
CONV
Digital Input
Digital Input
—
Digital Input
Digital Input
Digital
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
Test Mode Control
Resets the Digital Circuitry, Active Low
No Connection
Serial Data Input: Complementary Signal (optional, see text on page 13)
Serial Data Input
Digital Power Supply, 3V Nominal
Serial Data Clock Input: Complementary Signal (optional, see text on page 13)
Serial Data Clock Input
Master Clock Input
Data Valid Output, Active Low
Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A
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