參數(shù)資料
型號(hào): DDC114YK-7
廠商: DIODES INC
元件分類(lèi): 功率晶體管
英文描述: NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
中文描述: 70 mA, 50 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR
封裝: PLASTIC PACKAGE-6
文件頁(yè)數(shù): 27/30頁(yè)
文件大?。?/td> 389K
代理商: DDC114YK-7
""#
SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
27
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout
will ensure the best performance. It is essential to make
short, direct interconnections and avoid stray wiring
capacitance—particularly at the analog input pins. Digital
signals should be kept as far from the analog input signals
as possible on the PCB.
Input shielding practices should be taken into
consideration when designing the circuit layout for the
DDC114. The inputs to the DDC114 are high impedance
and extremely sensitive to extraneous noise. Leakage
currents between the PCB traces can exceed the input
bias current of the DDC114 if shielding is not implemented.
Figure 29 illustrates an acceptable approach to this
problem. A PC ground plane is placed around the inputs
of the DDC114. This shield helps minimize coupled noise
into the input pins.
This approach reduces leakage effects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather
than into the analog input stage of the DDC114.
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
IN4
IN3
Analog Ground
Digital I/O and Digital Power
Analog
Ground
Analog
Ground
Analog
Ground
IN2
IN1
37
24
DDC114
Analog Power
Figure 29. Recommended Shield for DDC114 Layout Design
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DDC118 制造商:BB 制造商全稱(chēng):BB 功能描述:Octal Current Input 20-Bit Analog-To-Digital Converter