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參數(shù)資料
| 型號： | DDC114TK-7 |
| 廠商： | DIODES INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR |
| 中文描述： | 100 mA, 50 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR |
| 封裝： | PLASTIC PACKAGE-6 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大小： | 389K |
| 代理商： | DDC114TK-7 |
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SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
12
DDC114 Frequency Response
The frequency response of the DDC114 is set by the front
end integrators and is that of a traditional continuous time
integrator, as shown in Figure 7. By adjusting T
INT
, the
user can change the 3dB bandwidth and the location of the
notches in the response. The frequency response of the
Σ
converter that follows the front end integrator is of no
consequence because the converter samples a held
signal from the integrators. That is, the input to the
Σ
converter is always a DC signal. Since the output of the
front end integrators are sampled, aliasing can occur.
Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down
to lower frequencies.
0
10
20
30
40
50
0.1
T
INT
100
T
INT
1
T
INT
10
T
INT
Frequency
G
Figure 7. Frequency Response of the DDC114
Test Mode
When Test Mode is used, the inputs (IN1, IN2, IN3, and
IN4) are disconnected from the DDC114 integrators to
enable the user to measure a zero input signal regardless
of the current supplied to the inputs. In addition, packets of
charge can be transferred to the integrators in 11pC
intervals to measure non-zero values. The test mode
works with both the continuous and non-continuous
modes. The timing diagram for the test mode is shown in
Figure 8 with the timing specifications given in Table 2.
To enter Test Mode, hold TEST high while CONV
transitions. If TEST is held high during the entire
integration period, the integrators measure a zero value.
This mode can be used to help debug a design or perform
diagnostic tests. To apply packets of charge during Test
Mode, simply strobe TEST low then high before the next
CONV transition. Each rising edge of TEST causes
approximately 11pC of charge to be transferred to the
integrators. This charge transfer is independent of the
integration time. Data retrieval during Test Mode is
identical to normal operation. To exit Test Mode, take
TEST low and allow several cycles after exiting before
using the data.
t
1
t
3
t
4
t
4
t
6
t
5
t
2
Action
CONV
TEST
Integrate B
Integrate A
Test Mode Disabled
0pC into B
11pC into A
22pC into B
33pC into A
Test Mode Disabled
Test Mode Enabled: Inputs Disconnected
Integrate B
Integrate A
Figure 8. Timing Diagram of the Test Mode of the DDC114
Table 2. Timing for the DDC114 in the Test Mode
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
t3
Setup Time for Test Mode Enable
100
ns
Setup Time for Test Mode Disable
100
ns
Hold Time for Test Mode Enable
100
ns
t4
From Rising Edge of TEST to the Edge of CONV while Test Mode
Enabled
1
μ
s
t5
t6
Falling Edge to Rising Edge of TEST
1
μ
s
Rising Edge to Falling Edge of TEST
1
μ
s
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| DDC114TU-7-F | 功能描述:開關(guān)晶體管 - 偏壓電阻器 DUAL NPN 200mW RoHS:否 制造商:ON Semiconductor 配置: 晶體管極性:NPN/PNP 典型輸入電阻器: 典型電阻器比率: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 直流集電極/Base Gain hfe Min:200 mA 最大工作頻率: 集電極—發(fā)射極最大電壓 VCEO:50 V 集電極連續(xù)電流:150 mA 峰值直流集電極電流: 功率耗散:200 mW 最大工作溫度: 封裝:Reel |
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